Experimental characterisation of coaxial TSV transistor keep out zones

Three‐dimensional (3D) integration is an emerging technology that aims to achieve efficient packaging of the multifunctional silicon (Si) die within a single chip package. This system in package approach achieves connectivity between the individual Si die using through Si via (TSV) technology. Coaxial TSVs have emerged as the preferred 3D interconnect for high‐frequency packaging applications due to their superior high‐frequency electrical characteristics. The interconnect utilises a copper shield to prevent noise and unwanted signal coupling to occur within the Si substrate. However, a potential disadvantage of 3D integration is the large transistor keep‐out‐zones (KOZs) required to prevent transistor variability caused by thermally induced stress due to the copper‐based TSVs in the Si substrate. Currently, only analytical models exist that predict KOZs for various coaxial TSV configurations and determining the precise KOZ is critical to minimise interconnect footprint that results in increased costs due to reductions in Si die area for integrated circuit designers. For the first time, the work has characterised the thermomechanical behaviour of fabricated coaxial TSVs utilising the microRaman spectroscopy technique to define transistor KOZ for both analogue and digital circuital applications.