Ultra‐low leakage SRAM design with sub‐32 nm tunnel FETs for low standby power applications
Source abstract
Abstract
Tunnel‐field‐effect transistors (TFETs) operate by quantum band‐to‐band tunnelling and display a steeper subthreshold slope than MOSFETs which substantially diminishes the standby current. This work explores the TFET‐based SRAM utilisation for Low STandby Power applications. An 8 T TFET SRAM cell operating at V DD = 1 V, which, in contrast to other 6 T TFET SRAMs, is write‐disturb‐ and half‐selection‐free is proposed. Simulations based on 30 nm p‐ and n‐TFETs models relying on I D , C GS , C GD vs. V GS , and V DS look‐up tables extracted from TCAD, indicate that the proposed cell has a Read SNM and a Write SNM of 120 and 200 mV, respectively, which are well above state of the art values repotted in the literature. When utilised in an 128 × 128‐bit memory array the proposed cell enables read and write operation at 3.84 GHz and 806 MHz, respectively, and a cell leakage of less than 2fA/bit, which makes it an excellent choice for Internet of Things applications.
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Research context
OpenAlex topics: Semiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Integrated Circuits and Semiconductor Failure Analysis
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
Commissariat a l'Energie Atomique CEA‐LETI Grenoble France
Institut superieur d'electronique de Paris Paris France
Computer Engineering Laboratory Faculty of Electrical Engineering Mathematics and Computer Science Delft University of Technology Delft Netherlands
Indian Institute of Science Bangalore India
References (27)
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