journal article·2024-10-09

Reconfigurable Multilevel Storage and Neuromorphic Computing Based on Multilayer Phase-Change Memory

Lu Wang, Ge Ma, Senhao Yan, Xiaomin Cheng, Xiangshui Miao

ACS Applied Materials & Interfaces· Volume 16· Issue 40
Publisher page

Abstract

In the era of big data, the amount of global data is increasing exponentially, and the storage and processing of massive data put forward higher requirements for memory. To deal with this challenge, high-density memory and neuromorphic computing have been widely investigated. Here, a gradient-doped multilayer phase-change memory with two-level states, four-level states, and linear conductance evolution using different pulse operations is proposed. The mechanism of multilevel states is revealed through high-resolution transmission electron microscopy (HRTEM) and finite-element analysis (FEA), which show that the sequential phase change among different sublayers is realized due to the different physical properties of the sublayers with different doping concentrations. Taking advantage of the devices' linear conductance evolution characteristic, a handwritten digit (28 × 28 pixel) recognition task is implemented with a high learning accuracy of 93.46% by building a simulated artificial neural network made up of this gradient-doped multilayer phase-change memory. It is proved that this gradient-doped multilayer phase-change memory is capable of both binary multilevel digital storage and brain-inspired analog in-memory computing in the same device, enabling reconfigurable applications in the future.
Source: openalex_inverted_index · Quality: baseline

Research context

OpenAlex topics: Advanced Memory and Neural Computing · Phase-change materials and chalcogenides · Ferroelectric and Negative Capacitance Devices

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

Affiliations

School of Integrated Circuits, Hubei Key Laboratory for Advanced Memories, Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan 430074, China

Funding

National Key Research and Development Program of China · Hubei Engineering Research Center on Microelectronics · Major Program (JD) of Hubei Province · Hubei Key Laboratory of Advanced Memories

References (39)

Show source-provided references
1. 10.1126/science.aao018510.1126/science.aao0185 ↗
2. 10.1038/nnano.2015.2910.1038/nnano.2015.29 ↗
3. 10.1063/1.367244810.1063/1.3672448 ↗
4. 10.1109/JPROC.2020.300454310.1109/JPROC.2020.3004543 ↗
5. 10.1038/nature1453910.1038/nature14539 ↗
6. 10.1038/s41928-017-0006-810.1038/s41928-017-0006-8 ↗
7. 10.1088/0022-3727/46/9/09300110.1088/0022-3727/46/9/093001 ↗
8. 10.1109/JETCAS.2015.242649510.1109/JETCAS.2015.2426495 ↗
9. 10.1109/TED.2012.222796910.1109/TED.2012.2227969 ↗
10. Shulaker, M. M.; Wu, T. F.; Pal, A. In Monolithic 3D Integration of Logic and Memory: Carbon Nanotube FETs, Resistive RAM, and Silicon FETs, Paper Presented at: 2014 IEEE International Electron Devices Meeting; 15–17 December 2014; IEEE: San Francisco, CA, USA, 2014.10.1109/IEDM.2014.7047120 ↗
11. Liauw, Y. Y.; Zhang, Z.; Kim, W.; Gamal, A. E.; Wong, S. S. In Nonvolatile 3D-FPGA with Monolithically Stacked RRAM-Based Configuration Memory, Paper Presented at: 2012 IEEE International Solid-State Circuits Conference; 19–23 February 2012; IEEE: San Francisco, CA, USA, 2012.10.1109/ISSCC.2012.6177067 ↗
12. 10.1109/JETCAS.2016.253329810.1109/JETCAS.2016.2533298 ↗
13. 10.1038/s41578-018-0076-x10.1038/s41578-018-0076-x ↗
14. 10.1111/ijag.1210710.1111/ijag.12107 ↗
15. 10.1146/annurev-matsci-082908-14540510.1146/annurev-matsci-082908-145405 ↗
16. 10.1109/JPROC.2010.207005010.1109/JPROC.2010.2070050 ↗
17. 10.1126/science.116023110.1126/science.1160231 ↗
18. 10.1039/D0TC01089H10.1039/D0TC01089H ↗
19. 10.1002/aelm.20210016410.1002/aelm.202100164 ↗
20. 10.1039/D1NR00100K10.1039/D1NR00100K ↗
21. 10.1063/1.291747110.1063/1.2917471 ↗
22. 10.1016/j.sse.2008.12.00310.1016/j.sse.2008.12.003 ↗
23. 10.1049/ell2.1233710.1049/ell2.12337 ↗
24. Nirschl, T.; Philipp, J. B.; Flapp, T. D. In Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory, Paper Presented at: 2007 IEEE International Electron Devices Meeting; 10–12 December 2007; IEEE: Washington, DC, USA, 2007.10.1109/IEDM.2007.4418973 ↗
25. 10.3390/mi1007046110.3390/mi10070461 ↗
26. 10.1021/nl201040y10.1021/nl201040y ↗
27. 10.1016/j.tsf.2015.04.01710.1016/j.tsf.2015.04.017 ↗
28. 10.1063/1.474214410.1063/1.4742144 ↗
29. 10.1038/s41427-020-0197-810.1038/s41427-020-0197-8 ↗
30. 10.1038/ncomms1004010.1038/ncomms10040 ↗
31. 10.1021/acsami.8b1847310.1021/acsami.8b18473 ↗
32. 10.1126/science.aay029110.1126/science.aay0291 ↗
33. 10.1109/LED.2022.320397110.1109/LED.2022.3203971 ↗
34. 10.1002/adfm.20210654710.1002/adfm.202106547 ↗
35. 10.1109/LED.2020.302827110.1109/LED.2020.3028271 ↗
36. 10.1109/5.72679110.1109/5.726791 ↗
37. 10.1016/j.patcog.2017.10.01310.1016/j.patcog.2017.10.013 ↗
38. Yu, S. M.; Chen, P. Y.; Cao, Y. In Scaling-Up Resistive Synaptic Arrays for Neuro-Inspired Architecture: Challenges and Prospect, Paper Presented at: 2015 IEEE International Electron Devices Meeting (IEDM); 07–09 December 2015; IEEE: Washington, DC, USA, 2015.10.1109/IEDM.2015.7409718 ↗
39. 10.1038/s41467-020-16108-910.1038/s41467-020-16108-9 ↗