Low-Temperature Co-hydroxylated Cu/SiO2 Hybrid Bonding Strategy for a Memory-Centric Chip Architecture
Source abstract
Abstract
Cu/SiO2 hybrid bonding with planarized dielectric and isolated metal connections can realize ultradense interconnects (e.g., ≤1 μm) by eliminating the microbumps and underfill through the direct bonding of Cu–Cu and SiO2–SiO2. However, the low-temperature bonding of Cu–Cu (oxide-free surface) and SiO2–SiO2 (hydroxylated surface) is difficult to be compatible in a mechanism. We circumvent this contradiction by constructing a co-hydroxylated functional surface on a Cu/SiO2 hybrid platform. By combining and optimizing the protocol of Ar/O2 plasma activation and formic acid solution immersion, an −OH active layer was successfully established on the Cu and SiO2 surfaces simultaneously, and the increased total surface area provided more adsorption sites for hydroxyl groups. A Cu–Cu interface with sufficient atom diffusion, substantial grain growth, and fewer microvoids was obtained at 200 °C. Notably, the carbon-related interlayer that may degrade the interfacial performance could be effectively inhibited across the optimized SiO2–SiO2 interface even if organic acid was introduced in the protocol. This low-temperature Cu/SiO2 hybrid bonding via a co-hydroxylated strategy may inspire the development of a memory-centric chip architecture and functional integrated circuits delivering a monolithic-like performance in the future hyperscaling era.
Source: openalex_inverted_index · Quality: baseline
Research context
OpenAlex topics: 3D IC and TSV technologies · Copper Interconnects and Reliability · Semiconductor materials and devices
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
State Key Laboratory of Advanced Welding and Joining, Harbin Institute of Technology, Harbin 150001, China
Funding
National Natural Science Foundation of China · Heilongjiang Provincial Natural Science Foundation of China
References (44)
Show source-provided references
1. 10.1038/nature2299410.1038/nature22994 ↗
2. 10.1038/s41565-020-0724-310.1038/s41565-020-0724-3 ↗
3. Lee, D. U.; Kim, K. W.; Kim, K. W.; Kim, H.; Kim, J. Y.; Park, Y. J.; Kim, J. H.; Kim, D. S.; Park, H. B.; Shin, J. W.; Cho, J. H.; Kwon, K. H.; Kim, M. J.; Lee, J.; Park, K. W.; Chung, B.; Hong, S. 25.2 A 1.2V 8Gb 8-Channel 128GB/s High-Bandwidth Memory (HBM) Stacked DRAM with Effective Microbump I/O Test Methods Using 29nm Process and TSV. In 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC); IEEE, 2014; pp. 432–433.10.1109/ISSCC.2014.6757501 ↗
4. Jeddeloh, J.; Keeth, B. Hybrid Memory Cube New DRAM Architecture Increases Density and Performance. In 2012 symposium on VLSI technology (VLSIT); IEEE, 2012; pp. 87–88.10.1109/VLSIT.2012.6242474 ↗
5. Peemen, M.; Setio, A. A. A.; Mesman, B.; Corporaal, H. Memory-Centric Accelerator Design for Convolutional Neural Networks. 2013 IEEE 31st Int. Conf. Comput. Des. ICCD 2013; IEEE 2013, No. 2013, 13–19.10.1109/ICCD.2013.6657019 ↗
6. Kwon, Y.; Rhu, M. Beyond the Memory Wall: A Case for Memory-Centric HPC System for Deep Learning. 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO); IEEE 2018, 2018-October, 148–161.10.1109/MICRO.2018.00021 ↗
7. Abdilla, J.; Bayer, U.; Boomsma, R.; Bulacher, S.; Kalss, A.; Martin, S.; Meixner, H.; Moura, T.; Selhofer, H.; Voegele, W.; Widauer, M. Thermo Compression Bonding for Large Dies under Protective Atmosphere. In 2020 IEEE 70th Electronic Components and Technology Conference (ECTC); IEEE, 2020; pp. 1277–1288.10.1109/ECTC32862.2020.00202 ↗
8. Enquist, P.; Fountain, G.; Petteway, C.; Hollingsworth, A.; Grady, H. Low Cost of Ownership Scalable Copper Direct Bond Interconnect 3D IC Technology for Three Dimensional Integrated Circuit Applications. In 2009 IEEE International Conference on 3D System Integration; IEEE, 2009; pp. 1–6.10.1109/3DIC.2009.5306533 ↗
9. Deo, M. Enabling Next-Gemeration Platforms Using Altera’s 3D System-in-Package Technology; Altera Inc. 2017, 1–7.
10. 10.1021/nl104469210.1021/nl1044692 ↗
11. Ibrahim M. · 2019
12. 10.1016/j.microrel.2011.03.03810.1016/j.microrel.2011.03.038 ↗
13. 10.1007/s10853-005-2677-110.1007/s10853-005-2677-1 ↗
14. 10.1063/1.326315410.1063/1.3263154 ↗
15. Yang, W.; Shintani, H.; Akaike, M.; Suga, T. Low Temperature Cu-Cu Direct Bonding Using Formic Acid Vapor Pretreatment. In 2011 IEEE 61st Electronic Components and Technology Conference (ECTC); IEEE, 2011; pp. 2079–2083.10.1109/ECTC.2011.5898804 ↗
16. 10.1088/0960-1317/23/4/04502510.1088/0960-1317/23/4/045025 ↗
17. 10.7567/JJAP.54.03021610.7567/JJAP.54.030216 ↗
18. 10.1016/j.apsusc.2014.10.09810.1016/j.apsusc.2014.10.098 ↗
19. 10.1116/1.138708410.1116/1.1387084 ↗
20. 10.1109/TADVP.2007.90639410.1109/TADVP.2007.906394 ↗
21. 10.1007/s11664-008-0489-110.1007/s11664-008-0489-1 ↗
22. Tong Q.-Y. · 1999
23. 10.1038/s41928-018-0117-x10.1038/s41928-018-0117-x ↗
24. 10.1038/s41586-020-2783-x10.1038/s41586-020-2783-x ↗
25. 10.1063/1.218546710.1063/1.2185467 ↗
26. 10.1016/S0040-6090(96)08807-410.1016/S0040-6090(96)08807-4 ↗
27. Yang, X.Y. Photoenergy and Thin Film Materials; John Wiley, 2019, 379–411.10.1002/9781119580546 ↗
28. 10.1143/JJAP.43.741510.1143/JJAP.43.7415 ↗
29. 10.3390/app701004910.3390/app7010049 ↗
30. 10.7598/cst2014.81610.7598/cst2014.816 ↗
31. 10.1016/j.apsusc.2015.01.04810.1016/j.apsusc.2015.01.048 ↗
32. 10.1007/s00542-018-4254-y10.1007/s00542-018-4254-y ↗
33. 10.1016/j.apsusc.2018.05.10910.1016/j.apsusc.2018.05.109 ↗
34. 10.1021/jz300510r10.1021/jz300510r ↗
35. Kagawa, Y.; Fujii, N.; Aoyagi, K.; Kobayashi, Y.; Nishi, S.; Todaka, N.; Takeshita, S.; Taura, J.; Takahashi, H.; Nishimura, Y.; Tatani, K.; Kawamura, M.; Nakayama, H.; Nagano, T.; Ohno, K.; Iwamoto, H.; Kadomura, S.; Hirayama, T. Novel Stacked CMOS Image Sensor with Advanced Cu2Cu Hybrid Bonding. In 2016 IEEE International Electron Devices Meeting (IEDM); IEEE, 2016; pp. 4–8.10.1109/IEDM.2016.7838375 ↗
36. 10.1016/j.apsusc.2018.06.20510.1016/j.apsusc.2018.06.205 ↗
37. 10.1021/jp970708910.1021/jp9707089 ↗
38. 10.1088/0953-8984/27/5/05400510.1088/0953-8984/27/5/054005 ↗
39. 10.1038/srep0973410.1038/srep09734 ↗
40. 10.1149/1.162699410.1149/1.1626994 ↗
41. 10.7567/JJAP.55.04EC0210.7567/JJAP.55.04EC02 ↗
42. 10.1149/2.0201607jss10.1149/2.0201607jss ↗
43. 10.1002/advs.20200376510.1002/advs.202003765 ↗
44. 10.1021/acs.jpclett.1c0142010.1021/acs.jpclett.1c01420 ↗