Trap-Enhanced Steep-Slope Negative-Capacitance FETs Using Amorphous Oxide Semiconductors

Amorphous oxide semiconductors (AOSs) have recently gained attention as a promising channel material of back-end-of-line (BEOL)-compatible transistors for monolithic three-dimensional (3D) integrations. However, the degradation in device performance resulting from the high trap densities in AOS, compared to conventional crystalline channel materials, has remained an intractable issue. We introduce the negative-capacitance (NC) operation into the AOS-based transistors. Negative-capacitance field-effect transistors (NCFETs) have been proposed for low-power devices, enabling sub-60 mV/decade subthreshold swing (SS) induced by a ferroelectric layer. In this work, we develop an AOS NCFET model to investigate the influence of traps within the channel on the steep-slope operation. It is revealed that as the trap density of the channel increases, SS of the MOSFET increases, while the SS of the NCFET decreases. The physical interpretation for steep SS is attributed to the fact that the trapped charges enhance the negative potential drop of the NC layer, enabling the abrupt device switching. This finding will accelerate the development of BEOL transistors and other applications based on the AOS materials in conjunction with the NC effect.