Dual-Parameter Variable Physically Unclonable Function (PUF) for Multilevel Cell Silicon MOSFETs

The rapid advancement of artificial intelligence (AI) has improved convenience but also introduced significant security risks. Physically unclonable functions (PUFs) have emerged as promising solutions to these challenges. In this study, we propose a multilevel cell (MLC)-based PUF that combines threshold voltage ( V TH ) and drain-induced barrier lowering (DIBL) within a single device. The statistical dependence between the two parameters was evaluated and quantified by employing conditional probabilities, entropy, mutual information (MI) and the Pearson correlation coefficient. To demonstrate this approach, single-crystalline silicon (single-Si) and polycrystalline silicon (poly-Si) channel metal oxide-semiconductor field-effect transistors (MOSFETs) were fabricated. The security of the proposed PUF was evaluated in terms of uniformity, interchip Hamming distance (HD inter ), and intrachip Hamming distance (HD intra ). This dual-parameter MLC scheme is compatible with monolithic integration, allowing compact cointegration of logic and security on a single chip. In particular, the poly-Si channel device supports low-temperature stacking, enabling direct integration of application processors (APs), dynamic random-access memory (DRAM), and static random-access memory (SRAM) circuits for broader system-level applicability.