Nanoscale Thermal Imaging of Local Subsurface Defects in Chips

Subsurface defects’ visualizations in chips become increasingly important as their feature sizes approach the subnanometer regime. In this study, a high-resolution contact resonance scanning thermal expansion microscopy (CR-STEM) was set up and employed to visualize the embedded defects inside the chips. Two types of defects with spot and line-like microstructures were clearly imaged by CR-STEM. The defect imaging contrast mechanism is attributed to different Joule thermal expansions of the buried structures due to their thermal resistance differences. Furthermore, the frequency-dependent behavior of defect imaging reveals depth-related profiles of subsurface defects. Local thermal stress fields are found to play an important role in the microstructural stability and reliability of the chip. These findings offer insights into the relationship between localized embedded structures and failure mechanisms in semiconductor devices.