High-Ge-Content Si_1–xGe_x Gate Stacks with Low-Temperature Deposited Ultrathin Epitaxial Si: Growth, Structures, Low Interfacial Traps, and Reliability

Si1–xGex with Ge contents higher than x = 0.5 is expected to boost on-current and improve reliability of p-channel metal-oxide-semiconductor (pMOS) devices. However, unavoidable GeOx formation at the high-κ/Si1-xGex interface with high Ge-contents (HGC) has caused high interfacial trap density, posing a challenge for employing the HGC Si1-xGex as the channel in sub-3 nm complementary MOS technology. In this work, we have deposited epitaxial Si (epi-Si) of six monolayer thickness on Si1–xGex at temperatures of 260–280 °C to minimize Ge diffusion and segregation. Si1–xGex layers with a wide range of HGC (0.5 < x ≤ 0.8) were grown to investigate the effectiveness of the epi-Si on the Si1–xGex. To minimize the GeOx formation caused by the oxidation of the segregated Ge on the epi-Si surface, HfO2 was subsequently deposited via e-beam evaporation on the epi-Si. The measurements using reflection high-energy electron diffraction, high-resolution synchrotron radiation X-ray diffraction, and scanning transmission electron microscopy with high-angle annular-dark-field imaging have revealed the high crystallinity of the epi-Si, the Si1–xGex layers, and abrupt interfaces of the high-κ/epi-Si/Si1–xGex layers. The well-controlled interfaces have enabled the achievement of low interfacial trap densities (Dit) of (3–6) × 1011 eV–1 cm–2 in these high-κ/epi-Si/(HGC)Si1–xGex samples. The minimum Dit values remained at 3 × 1011 eV–1 cm–2 regardless of the Ge content, confirming the effective passivation of the low-temperature deposited epi-Si. By extracting the effective charge sheet densities for the Si1–xGex gate stacks via examination of capacitance–voltage (C–V) hysteresis with decreasing stress voltage in the accumulation region of the MOS capacitors, we have attained very high acceleration factors of 8–12, indicating high reliability of the HfO2/epi-Si/SiGe pMOS gate stacks.