Ultralow Saturation Voltage in WS₂ Source-Gated Transistors with Self-Aligned and Fermi-Level-Depinned Contacts

Transition-metal dichalcogenides (TMDs) have emerged as promising materials for overcoming the scaling limitations of conventional silicon-based electronics. However, achieving efficient current saturation at low operating voltages remains challenging for field-effect transistors based on TMDs. In this study, we develop a WS 2 -based tunnel-contact source-gated transistor (TC-SGT) using a self-aligned contact process with a T-shaped source electrode. This approach allows the formation of a sub-400 nm channel without additional lithography steps, simplifying the fabrication process. A 2 nm Al 2 O 3 layer inserted at the WS 2 –metal interface significantly reduces the Fermi-level pinning, increasing the Schottky barrier height from 48.5 to 90.0 meV. This configuration enables contact-controlled operation with an ultralow saturation voltage of 0.12 V, which is the lowest value reported among TMD-based transistors. The TC-SGT exhibits ultralow power consumption of 1.2 nW and a high intrinsic gain of 364. Notably, the TC-SGT maintains stable current saturation across various channel lengths and temperatures down to 160 K, demonstrating its suitability for ultrascaled and low-power electronics. This approach enables full utilization of the unique TMD properties, thus providing a promising platform for postsilicon integrated circuits.