Comparative Study of Different Configurations in Triple-Sided Charged Plasma Symmetric Lateral Heterojunction Bipolar Transistors on SOI
Source abstract
Abstract
A comparative simulation study of triple-sided charged plasma symmetric lateral heterojunction bipolar transistors (3SCP SLHBTs) on SOI is performed for the first time. A 3SCP SLHBT has all the advantages that a conventional charge plasma (cCP) lateral bipolar on SOI has, namely, overcoming the issue related to the thermal budget along with improvements in current gain and speed. Our new design along with the heterojunction configuration is able to further improve upon the performance of cCP design by inducing carriers from the bottom, side, and top with respect to cCP design where the carrier concentration is low toward the bottom region of the active device layer. Our novel 3SCP SLHBT design shows huge improvements in current gain, fT, and fmax by almost 1092, 80.6, and 51.6% respectively with repsect to cCP SLHBT design. In this article, we carried out a systematic study of the heterojunction bipolar structure of the 3SCP device design with three different HBT configurations and presented a comparative study of their performance. The different 3SCP SLHBT configurations studied here as emitter-base-collector are Si-0.3Ge-Si, Si-linearly graded SiGe-Si, and Si-Ge-Si, respectively. We are able to achieve the same collector current but with a lower VBE by ∼320 mV when a device having a Si-linearly graded SiGe-Si configuration is replaced with a device having a Si-Ge-Si configuration. We are able to achieve and demonstrate this novel HBT device with the best optimal performance parameters for the Si-0.3Ge-Si configuration. This device shows a current gain of 8.4 × 105, with fT = 428.87 GHz and fmax = 2.38 THz. We are also able to successively demonstrate the symmetric complementary 3SCP SLHBT inverter using the Si-0.3Ge-Si configuration having optimal digital circuit performance parameters. The inverter has a switching voltage (VM) of 0.505 V, a low noise margin (NML) of 0.47 V, and a high noise margin (NMH) of 0.45 V at 1 V.
Source: openalex_inverted_index · Quality: baseline
Research context
OpenAlex topics: Advancements in Semiconductor Devices and Circuit Design · Quantum and electron transport phenomena · Semiconductor materials and devices
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
School of Computer & Systems Sciences, Jawaharlal Nehru University, New Delhi 110067, India
Funding
University Grants Commission · Department of Science and Technology, Ministry of Science and Technology
References (38)
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