Ab Initio Quantum Transport Simulations of the Sub-3 nm Gate-Length Monolayer CuBr Transistors for High-Performance Device Applications

As the physical thickness of silicon decreases, the effective carrier mobility (μ) degrades significantly, leading to a substantial reduction in the performance of field-effect transistors (FETs). In this context, two-dimensional (2D) semiconductors have emerged as promising channel materials for next-generation transistors owing to their atomic-scale thickness and intrinsically high carrier mobility. In 2D materials, monolayer (ML) CuBr exhibits an atomic-layer thickness similar to graphene and demonstrates carrier mobilities of 1153.54 cm 2 V –1 s –1 for electrons (μ e ) and 15.88 cm 2 V –1 s –1 for holes (μ h ), which are higher than those of many other 2D semiconductors, such as MoS 2 (∼200 cm 2 V –1 s –1 ) and BN (∼487 cm 2 V –1 s –1 ). Leveraging the atomic-scale thickness with high electron mobility of ML-CuBr, we performed quantum transport simulations to evaluate the performance limits of the sub-3 nm gate-length ( L g ) double-gated (DG) n-type FETs for high-performance (HP) device applications. Our simulation results show that the ML-CuBr n-type FETs outperform the requirements set by the international technology roadmap for semiconductors (ITRS) for the 2028 horizon technology node. Notably, at L g = 3 nm, the device demonstrates high I on of 1372 μA/μm, ultralow subthreshold swing (SS) of 45 mV/dec, transconductance ( g m ) of 5.62 mS/μm, time-delay (τ) of 0.337 ps, power-delay product (PDP) of 0.246 fJ/μm, and energy-delay product (EDP) of 8.29 × 10 –29 Js/μm. These findings establish ML-CuBr as a highly promising channel material capable of enabling ultrascaled, energy-efficient transistors for high-performance device applications.