Tapping the Performance of a Tungsten Disulfide Field-Effect Transistor with Deep Structure Optimization and Theoretical Simulation

As a representative material for two-dimensional transition metal dichalcogenides (2D TMDCs), tungsten disulfide (WS 2 ) has a theoretical carrier mobility of up to 10 3 cm 2 ·V –1 ·s –1 at room temperature (298 K) and is expected to be an excellent channel material for transistors. Meanwhile, the thickness of WS 2 and the substrate thickness have an important impact on transistor performance. However, until now, despite extensive research on WS 2 -based field-effect transistors (WS 2 -FETs), WS 2 -FET performance has not been fully explored due to the large random thickness of WS 2 nanosheets prepared using mechanical peeling methods and the lack of systematic studies on the preparation and testing of FET conditions and theoretical analysis, thus considerably limiting the application and development of WS 2 -FETs. In this study, we prepared FETs based on high-quality WS 2 nanosheets via micromechanical exfoliation and investigated the factors influencing their performance. The optimum electrical properties of the WS 2 -FETs were obtained by regulating the thickness of the WS 2 nanosheet and dielectric layer substrate and the annealing treatment, combined with theoretical simulation analysis. The resulting 9-layer WS 2 nanosheets exhibited the best electrical properties, with a carrier mobility at 298 K of 531.41 cm 2 ·V –1 ·s –1 . The results of this study provide a basis for further research and optimization of high-performance logic devices based on 2D TMDCs.