Short-Channel Features and Channel Length Guideline in High-Resolution Display Panel Oxide Transistors

Scaling of accumulation-mode amorphous indium–gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) is increasingly important but seems not easy with a decreased cell size. It is because oxygen-vacancy donors may uncontrollably shorten channel length ( L ch ) by a lateral extension (2Δ L ) during an n + source/drain (S/D) forming process, causing short-channel effects (SCE). A minimum L ch guideline is thus necessary based on Δ L estimation. Here, industry-fabricated a-IGZO TFTs with nominal channel lengths of 2.5 to 10 μm were analyzed to extract an effective length, L eff (≡ L ch –2Δ L ). The threshold voltage ( V th ) of our a-IGZO TFTs has rarely shifted until L ch is reduced to ∼3 μm; however, further scaling to L ch = 2.5 μm, the V th appears to drastically shift to a negative voltage. Concomitantly, serious drain-induced barrier lowering (DIBL) is observed for devices with an L ch of 2.5 μm. We attribute such SCE features to 2Δ L -reduced channel length, L eff, because an estimated 2Δ L appears over 1.5 μm. Finally, through experiments and Poisson’s equation treatment for incipient accumulation, we first suggest a practical L eff guideline that enables reliable device operations: minimum L eff = ∼0.96 μm and a nominal L ch ≥ 3 μm.