Abnormal Threshold Voltage Shift and Sub-channel Generation in Top-Gate InGaZnO TFTs under Backlight Negative Bias Illumination Stress

Previous reports on the top-gate IGZO thin-film transistors (TFTs) under negative bias illumination stress (NBIS) show a threshold voltage ( V TH ) shift to the left. However, in the present study, a right shift in V TH was observed in the reverse-sweep current–voltage ( I – V ) curves after applying NBIS to top-gate IGZO TFTs by a UV backlight. The hysteresis window of the forward and reverse sweep I – V curves widened with the increase in the stress time. The abnormal V TH shift and hysteresis-window increment are explained using an energy-band diagram. In addition, an abnormal g m peak appeared in the forward I – V curve after 2000 s of the backlight NBIS, which was verified by testing the devices with different dimensions. Silvaco TCAD simulation results indicated a strong electric field in the sidewall, confirming the generation of sub-channels. The comparison of the Δ V TH after UV backlight NBIS in three different devices suggested that the higher N 2 O/SiH 4 flow rate and lower power deposition can produce a good quality buffer layer. A rapid examination of a buffer layer is possible using the backlight NBIS. In addition, the presence of H 2 in the buffer layer was confirmed by the thermal desorption spectroscopy. Finally, the reliability of the devices can be enhanced by improving the modulation of the existing deposition process.