Top-Gate Stack Engineering Featuring a High-κ Gadolinium Aluminate Interfacial Layer for Field-Effect Transistors Based on Two-Dimensional Transition-Metal Dichalcogenides

Atomic layer deposition (ALD) of gate dielectrics on two-dimensional transition-metal dichalcogenides (2D TMDs) is challenging due to their chemically inert surfaces. Although various surface pretreatments can form nucleation sites to facilitate the precursor adsorption, preserving 2D TMDs during the pretreatments and maintaining gate stack quality with the weak 2D TMD/dielectric interface become the main concerns. In this work, we combine physisorbed-precursor-assisted (PPA)-ALD to minimize damage to 2D TMDs with a second interfacial layer for performance enhancement. Ultrathin GdAlO 3 interlayers are integrated into 2D TMD gate stacks with PPA-ALD AlO x seeding layers and HfO 2 top dielectrics. Further, 1-nm-thick and pinhole-free GdAlO 3 can be deposited on AlO x -seeded monolayer (1L) WS 2 by ALD at 250 °C. The material properties of 1L WS 2 are preserved, as confirmed by Raman spectroscopy. After the GdAlO 3 layer insertion, 1L MoS 2 dual-gate (DG) field-effect transistors (FETs) show improved subthreshold swing (SS), field-effect mobility, and I d – V g hysteresis without compromising the capacitance-equivalent thickness (CET). The proposed strategy is wafer-scale compatible and extendable to the future nanosheet gate-all-around structures.