3 nm Channel MoS₂ Transistors by Electromigration of Metal Interconnection

Further scaling down the feature size of transistors is central for the development of next-generation electronic devices. However, fabrication of transistors with channel lengths down to 5 nm has been challenging due to lithography limit and short channel effects (SCEs). Here, we demonstrate an MoS 2 -based device with the shortest 3 nm channel length among global back-gated transistors by feedback-controlled electromigration of metal interconnection. The Si/SiO 2 -back-gated model device shows on/off ratios of up to 2 × 10 5 and exhibits a field-effect mobility of up to 33.5 cm 2 V –1 s –1, which is, to the best of our knowledge, the highest value in the as-yet-reported same-type transistors with a sub-10 nm channel length. This good immunity of the device to SCEs is also corroborated by the COMSOL Multiphysics simulation. After replacing the thicker physical gate SiO 2 dielectric and Si electrode with the 2D hexagonal boron nitride (h-BN) and graphene monolayer, respectively, for better gate control, the field-effect mobility is pushed to 51.2 cm 2 V –1 s –1 and displays excellent switching characteristics with near-ideal subthreshold swing of 67 mV dec –1 and drain-induced barrier lowering as low as 0.378 V V –1 . This work can promote further transistor downscaling and extend Moore’s law.