Fabrication Strategies of Metal–Ferroelectric–Insulator–Silicon Gate Stacks Using Ferroelectric Hf–Zr–O and High-k HfO₂ Insulator Layers for Securing Robust Ferroelectric Memory Characteristics

Metal–ferroelectric–insulator–Si (MFIS) gate stack structures were fabricated and characterized to investigate the optimum process indicators when HfO2-based thin films were exploited as the ferroelectric layer (FL) for the ferroelectric-field-effect-driven nonvolatile memory operations. The interfacial transition layer thicknesses of the metal–insulator–semiconductor capacitors using high dielectric constant (high-k) insulator layers (ILs) were preliminarily examined to be approximately 0.7 and 0.5 nm for the Pt/HfO2/Si and Pt/Al2O3/Si capacitors, respectively, which corresponded to Hf silicate and amorphous SiO2. As the result, the introduction of HfO2 IL was verified to enhance the capacitance coupling ratio 1.7 times higher than that by the use of Al2O3 IL for the MFIS devices. Alternatively, among the fabricated MFIS capacitors with various combinations of high-k ILs and HfO2-based FLs, the counterclockwise hysteresis loops supported by ferroelectric field effects in the C–V curves were obtained only from the devices employing the HfZrO (HZO) FLs and HfO2 ILs. Especially, when the film thicknesses of the HZO FL and HfO2 IL were controlled to be 20 and 5 nm, respectively, the MFIS capacitor exhibited the ferroelectric memory window as large as 2.1 V and the long-term retention with a charge loss of only 11% after a lapse of time for 104 s. These differences in the device characteristics among the controlled devices originated from the combined effects of voltage distribution between the FLs and ILs, crystallinity of the FL prepared on various ILs, and capacitance coupling ratio, which could be suggested as important control parameters to optimize the memory operations of MFIS devices.