journal article·2020-02-25

Field Effect Transistor-Type Devices Using High-κ Gate Insulator Stacks for Neuromorphic Applications

Min-Kyu Park, Ho-Nam Yoo, Young-Tak Seo, Sung Yun Woo, Jong-Ho Bae, Byung-Gook Park, Jong-Ho Lee

Publisher page

Abstract

With ability to process data in an energy-efficient way, neuromorphic computing is suggested to overcome the issues of a traditional von Neumann computing system. Neuromorphic computing is composed of two crucial features of neurons and synapses, in which neurons integrate all the charges while synapses retain these charges. In this paper, we fabricate and analyze devices for mimicking neurons and synapses in a single Si-based metal-oxide-semiconductor field-effect transistor (MOSFET) structure. We fabricate and analyze Al2O3/Si3N4 (A/N) and Al2O3/HfO2/Si3N4/SiO2 (A/H/N/O) devices to suggest that an A/N device could be used as a neuron device due to its fast charge emission characteristics, while the A/H/N/O device could be used as a synaptic device as added tunneling SiO2 causes the device to retain its charges for a long-period of time. We suggest the possibility of fabricating both neurons and synapses by adopting different gate insulator stack structures in MOSFETs.
Source: openalex_inverted_index · Quality: baseline

Research context

OpenAlex topics: Advanced Memory and Neural Computing · Semiconductor materials and devices · Ferroelectric and Negative Capacitance Devices

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

Affiliations

Department of Electrical and Computer Engineering and ISRC, Seoul National University, Seoul, 08826, Korea

Department of Electrical and Computer Sciences, University of California at Berkeley, Berkeley, California 94720, United States

Funding

National Research Foundation of Korea · Ministry of Trade, Industry and Energy

References (15)

Show source-provided references
1. 10.1109/JPROC.2015.244409410.1109/JPROC.2015.2444094 ↗
2. 10.3389/fnins.2011.0010810.3389/fnins.2011.00108 ↗
3. 10.1212/01.WNL.0000166914.38327.BB10.1212/01.WNL.0000166914.38327.BB ↗
4. Corsi, P. M. Human memory and the medial temporal region of the brain. Dissertation, McGill University, Montreal, 1973.
5. 10.3389/fnins.2011.0007310.3389/fnins.2011.00073 ↗
6. Wu, M.H.; Hong, M.C.; Chang, C.C.; Sahu, P.; Wei, J.H.; Lee, H.Y.; Shcu, S.S.; Hou, T.H. Extremely Compact Integrate-and-Fire STT-MRAM Neuron: A Pathway toward All-Spin Artificial Deep Neural Network. 2019 Symposium on VLSI Technology, Kyoto, Japan, June 9–14, 2019.10.23919/VLSIT.2019.8776569 ↗
7. Cantley K. D. · 2011
8. 10.1021/acsnano.7b0334710.1021/acsnano.7b03347 ↗
9. 10.3389/fnins.2016.0005610.3389/fnins.2016.00056 ↗
10. Hamdioui, S.; Aziza, H.; Sirakoulis, G. C. Memristor Based Memories: Technology, Design and Test. 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Santorini, Greece, May 6–8, 2014.10.1109/DTIS.2014.6850647 ↗
11. 10.1109/TED.2018.288887110.1109/TED.2018.2888871 ↗
12. 10.1109/TED.2014.237875810.1109/TED.2014.2378758 ↗
13. 10.1152/jn.00190.200410.1152/jn.00190.2004 ↗
14. Schuegraf, K.; Park, D.; Hu, C. Reliability of Thin SiO/Sub 2/ at Direct-Tunneling Voltages. Proceedings of 1994 IEEE International Electron Devices Meeting. San Francisco, California, December 11–14, 1994.
15. Chen, C.; Yang, M.; Liu, S.; Liu, T.; Zhu, K.; Zhao, Y.; Wang, H.; Huang, Q.; Huang, R. Bio-Inspired Neurons Based on Novel Leaky-FeFET with Ultra-Low Hardware Cost and Advanced Functionality for All-Ferroelectric Neural Network. 2019 Symposium on VLSI Technology. Kyoto, Japan, June 9–14, 2019.10.23919/VLSIT.2019.8776495 ↗