journal article·2025-03-25Open access

High-Performance Silicon Nanowire Reconfigurable Field Effect Transistors Using Flash Lamp Annealing

Sayantan Ghosh, Muhammad Bilal Khan, Slawomir Prucnal, René Hübner, Phanish Chava, Tom Mauersberger, Thomas Mikolajick, Artur Erbe, Yordan M. Georgiev

Abstract

High Resolution Image Download MS PowerPoint Slide Top-down fabrication of reconfigurable field effect transistors (RFET) is a prerequisite for large-scale integration. Silicon (Si) nanowire-based RFET devices have been extensively studied in the past decade. To achieve superior RFET performance, it is necessary to develop scalable devices with controlled silicidation of the channels, a high on–off ratio, and symmetrical p- and n- on-currents. In this work, we present the electrical performance of scalable RFET devices based on Si nanowires featuring controlled silicide lengths attained through millisecond-range flash lamp annealing (FLA). The electronic properties of the transistors are optimized by tuning the different gate schemes and gate dielectric materials for nanowire passivation. We explore gate capacitive control on the energy bands in the conduction of charge carriers using various dielectric materials. The transfer characteristics of a single top-gated device with SiO 2 as gate dielectric show enhanced ambipolar behavior with negligible hysteresis, low subthreshold swing values of 210 mV/dec, and an on–off ratio ( I ON / I OFF ) of up to ∼10 8 (8 orders of magnitude). The devices also demonstrate excellent electron and hole symmetry values with a record pn on-current symmetry of 1.03. Utilizing high-performance, scalable RFET devices with elevated symmetrical on-currents holds great promise for reducing delay and power consumption in future energy-efficient integrated circuitry.
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Research context

OpenAlex topics: Semiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Nanowire Synthesis and Applications

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

Affiliations

Institute of Ion Beam Physics and Materials Research, Helmholtz-Zentrum Dresden-Rossendorf (HZDR), Bautzner Landstraße 400, Dresden 01328, Germany

Technische Universität Dresden

Namlab gGmbH, Nöthnitzer Strasse 64, Dresden 01187, Germany

Technische Universität Dresden, Center for Advancing Electronics Dresden (CfAED)

Institute of Electronics at the Bulgarian Academy of Sciences, 72, Tsarigradsko chaussee blvd., Sofia 1784, Bulgaria

Funding

Horizon 2020 Framework Programme

References (75)

Show source-provided references
1. 10.1126/science.285.5436.207910.1126/science.285.5436.2079 ↗
2. 10.3389/fmats.2023.122453710.3389/fmats.2023.1224537 ↗
3. 10.1146/annurev.ms.24.080194.00131510.1146/annurev.ms.24.080194.001315 ↗
4. 10.1016/S0039-6028(01)01558-810.1016/S0039-6028(01)01558-8 ↗
5. 10.1103/RevModPhys.76.32310.1103/RevModPhys.76.323 ↗
6. 10.1088/0022-3727/39/21/R0110.1088/0022-3727/39/21/R01 ↗
7. 10.1002/adma.20080375410.1002/adma.200803754 ↗
8. 10.1063/1.12625710.1063/1.126257 ↗
9. Cao, W.; Kang, J.; Liu, W.; Khatami, Y.; Sarkar, D.; Banerjee, K. In 2D Electronics: Graphene and Beyond, Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2013; pp 37–44.10.1109/ESSDERC.2013.6818814 ↗
10. 10.1038/s41586-021-03339-z10.1038/s41586-021-03339-z ↗
11. 10.1126/science.115887710.1126/science.1158877 ↗
12. Mertens, H.; Ritzenthaler, R.; Chasin, A.; Schram, T.; Kunnen, E.; Hikavyy, A.; Ragnarsson, L.Å.; Dekkers, H.; Hopf, T.; Wostyn, K. In Vertically Stacked Gate-all-around Si Nanowire CMOS Transistors with Dual Work Function Metal Gates, IEEE International Electron Devices Meeting (IEDM), 2016; pp 19.7.1–19.7.4.10.1109/IEDM.2016.7838456 ↗
13. 10.1021/nl203094h10.1021/nl203094h ↗
14. 10.1016/j.sse.2014.06.01010.1016/j.sse.2014.06.010 ↗
15. 10.1088/1361-6641/aa558110.1088/1361-6641/aa5581 ↗
16. 10.1021/acsami.3c0480810.1021/acsami.3c04808 ↗
17. 10.3390/app917346210.3390/app9173462 ↗
18. 10.1109/LED.2020.299731910.1109/LED.2020.2997319 ↗
19. 10.1021/nl061385810.1021/nl0613858 ↗
20. 10.1038/nature0267410.1038/nature02674 ↗
21. 10.1021/acs.langmuir.1c0186210.1021/acs.langmuir.1c01862 ↗
22. 10.1103/PhysRevB.24.335410.1103/PhysRevB.24.3354 ↗
23. Rhoderick E. H. · 1988 · 129
24. 10.1063/1.485840010.1063/1.4858400 ↗
25. Kang, S.M. Yusuf Leblebici: CMOS Digital Integrated Circuits2003.
26. 10.1063/1.215058110.1063/1.2150581 ↗
27. Zhang, M.; Knoch, J.; Zhao, Q.; Breuer, U.; Mantl, S. In Schottky Barrier Height Modulation Using Dopant Segregation in Schottky-Barrier SOI-MOSFETs, Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005, 2005; pp 457–460.10.1109/ESSDER.2005.1546683 ↗
28. 10.1063/1.186344210.1063/1.1863442 ↗
29. 10.1016/j.sse.2016.10.00910.1016/j.sse.2016.10.009 ↗
30. 10.1021/nl401826u10.1021/nl401826u ↗
31. 10.1063/1.165704310.1063/1.1657043 ↗
32. Sze S. M. · 2021
33. 10.1063/1.369067010.1063/1.3690670 ↗
34. 10.1021/am300288z10.1021/am300288z ↗
35. 10.1109/TNANO.2016.254252510.1109/TNANO.2016.2542525 ↗
36. 10.1002/pssc.20077657810.1002/pssc.200776578 ↗
37. Wallace, R. M.Dielectric Materials for Microelectronics. Springer Handb. Electron. Photonic Mater. 2017, pp 1 10.1007/978-3-319-48933-9_27.10.1007/978-3-319-48933-9_27 ↗
38. 10.1116/1.58666110.1116/1.586661 ↗
39. 10.1063/1.11075810.1063/1.110758 ↗
40. 10.1021/nl801185310.1021/nl8011853 ↗
41. 10.1143/JJAP.37.395410.1143/JJAP.37.3954 ↗
42. 10.1143/JJAP.46.327710.1143/JJAP.46.3277 ↗
43. 10.1016/j.sse.2003.12.01910.1016/j.sse.2003.12.019 ↗
44. 10.1021/nl103156q10.1021/nl103156q ↗
45. 10.1088/0957-4484/22/36/36530510.1088/0957-4484/22/36/365305 ↗
46. 10.1007/s11664-009-1071-110.1007/s11664-009-1071-1 ↗
47. 10.1016/j.tsf.2011.08.03410.1016/j.tsf.2011.08.034 ↗
48. Appenzeller, J.; Knoch, J.; Tutuc, E.; Reuter, M.; Guha, S. In: Dual-Gate Silicon Nanowire Transistors With Nickel Silicide Contacts, 2006 International Electron Devices Meeting, 2006; pp 1–4.10.1109/IEDM.2006.346842 ↗
49. 10.1063/1.499919510.1063/1.4999195 ↗
50. 10.1016/j.mee.2010.11.01110.1016/j.mee.2010.11.011 ↗
51. 10.1088/0034-4885/69/2/R0210.1088/0034-4885/69/2/R02 ↗
52. 10.1116/1.481842610.1116/1.4818426 ↗
53. 10.3390/ma1324580910.3390/ma13245809 ↗
54. 10.1088/1674-4926/35/4/04400110.1088/1674-4926/35/4/044001 ↗
55. 10.1007/s11664-024-11332-110.1007/s11664-024-11332-1 ↗
56. 10.7567/JJAP.53.06JG0410.7567/JJAP.53.06JG04 ↗
57. 10.1063/1.32536810.1063/1.325368 ↗
58. 10.1109/TNANO.2017.269496910.1109/TNANO.2017.2694969 ↗
59. 10.1109/TED.2010.209277910.1109/TED.2010.2092779 ↗
60. 10.1021/jp000930510.1021/jp0009305 ↗
61. 10.1038/s41467-022-34533-w10.1038/s41467-022-34533-w ↗
62. 10.1063/5.003602910.1063/5.0036029 ↗
63. 10.1109/LED.2023.334739710.1109/LED.2023.3347397 ↗
64. 10.1109/TED.2023.334636110.1109/TED.2023.3346361 ↗
65. 10.1109/TED.2014.235911210.1109/TED.2014.2359112 ↗
66. Sessi, V.; Simon, M.; Slesazeck, S.; Drescher, M.; Mulaosmanovic, H.; Li, K.; Binder, R.; Waidmann, S.; Zeun, A.; Pawlik, A.S.S2–2 Back-bias Reconfigurable Field Effect Transistor: A Flexible Add-on Functionality for 22 nm FDSOI. 2021 Silicon Nanoelectronics Workshop (SNW). 2021, pp 1–2.
67. De Marchi, M.; Sacchetto, D.; Frache, S.; Zhang, J.; Gaillardon, P.E.; Leblebici, Y.; De Micheli, G. In: Polarity Control in Double-Gate, Gate-all-around Vertically Stacked Silicon Nanowire FETs. 2012 International Electron Devices Meeting. 2012; pp 8–4.10.1109/IEDM.2012.6479004 ↗
68. 10.1109/JEDS.2024.335020910.1109/JEDS.2024.3350209 ↗
69. 10.1021/acsnano.6b0753110.1021/acsnano.6b07531 ↗
70. Beyer, C.; Bhattacharjee, N.; Mikolajick, T.; Trommer, J. Back-Bias Effects in a SiGe Nanosheet Transistor with Multiple Independent Gates. Adv. Mater. Technol. 2024, p 2401391. 10.1002/admt.202401391.10.1002/admt.202401391 ↗
71. 10.1002/aelm.20220125910.1002/aelm.202201259 ↗
72. 10.1016/j.pisc.2016.06.08110.1016/j.pisc.2016.06.081 ↗
73. 10.1109/5.37196410.1109/5.371964 ↗
74. Ghosh, S.; Echresh, A.; Khan, M.; Bhattacharya, D.; Kentsch, U.; Prucnal, S.; Vardhan, V.; Biswas, S.; Hellebust, S.; Wenger, J.; Holmes, J.; Erbe, A.; Georgiev, Y. In: Polarity Control in Doped Silicon Junctionless Nanowire Transistor for Sensing Application. 2024 Device Research Conference (DRC). 2024; pp 1–2.10.1109/DRC61706.2024.10605574 ↗
75. 10.1116/1.160328410.1116/1.1603284 ↗