Interface-Engineered HfO₂/Al₂O₃ Nanolaminate Gate Insulators for InGaZnO Thin-Film Transistors and 2T0C DRAM Applications

The effect of gate insulator (GI) structure on the device characteristics of oxide semiconductor thin-film transistors (TFTs) and the suitability of the 2T0C DRAM cell is investigated. Three types of GI are compared: single-layer HfO 2, nanolaminate-stacked HfO 2 /Al 2 O 3, and double-layered laminate-stacked HfO 2 /Al 2 O 3 . The laminate films suppressed crystallization and minimized defect formation, whereas the single-layer HfO 2 films exhibited crystallization and increased oxygen-related defects. The InGaZnO TFT utilizing laminate GI structures exhibited improved subthreshold swing (SS), diminished hysteresis in drain current, improved dielectric reliability, and enhanced bias-stress stability compared to that employing the single-layer HfO 2 . When integrated into 2T0C DRAM cells, the laminate GI configurations were demonstrated to enable effective charge storage and data retention for longer than 10 3 s at low-voltage operation. These findings suggest that the laminated GI provides a promising design strategy for next-generation low-power memory devices based on oxide semiconductors.