Short-Channel Effect Suppression and Footprint Reduction in Double Gate-All-Around Field Effect Transistors and Inverters Based on Two-Dimensional Materials

The incessant reduction of transistor dimensions requires new transformations in devices or novel materials to further sustain Moore’s law. From the 5 nm technology node and beyond, the gate-all-around field effect transistor (GAAFET) dominates the semiconductor industry, owing to its ultimate gate electrostatic controllability. Two-dimensional (2D) materials possess the merits of dangling-bond-free surfaces, atomic thicknesses down to sub-1 nm, and high mobility maintenance at sub-1 nm thickness, which are challenges long plaguing traditional three-dimensional (3D) semiconductors. Herein, we devised a double-gated GAAFET (DG GAAFET) based on monolayer MoS 2 . Compared with a DG GAAFET based on Si with the same footprint, the MoS 2 DG GAAFET demonstrates the capability of suppressing short-channel effects out of the regime of the Si DG GAAFET, though a relatively small I on value, which is attributed to the lower density of states, has been obtained in the monolayer MoS 2 DG GAAFET. A single-gated GAAFET based on monolayer MoS 2 (MoS 2 SG GAAFET) has also been simulated as a control device, which manifests an inferior device performance and degraded short-channel effects compared to those of the MoS 2 DG GAAFET, which are revealed by larger SS and a reduced I on / I off ratio. It is verified to be feasible to surge I on by 84% without short-channel effect degradation via the incorporation of an additional channel, bobbing well for the application of the DG GAAFET device based on 2D materials in high-performance electronics. Besides, a logic inverter based on a double-channeled double-gated GAAFET (DG DC GAAFET) based on WSe 2 and MoS 2 has been simulated, and a voltage gain of 36 has been obtained under a gate voltage of 2 V. Moreover, an additional degree of freedom can be introduced by adding a SiO 2 interlayer, which contributes to the subthreshold voltage matching between a MoS 2 n-type transistor and a WSe 2 p-type transistor, where a voltage gain of 45 at a gate voltage of 2 V has been obtained. Both the above complementary metal–oxide–semiconductor (CMOS) inverter structures can make full play of the inner areas of the GAA structure, which sheds light on the footprint decrease of inverters, leaving room for more electronics to be crammed into a single chip.