Interface and Border Traps in the Gate Stack of Carbon Nanotube Film Transistors with an Yttria Dielectric

Measurement and optimization of interface states in metal oxide semiconductors are the premise of building high-performance and high-reliability field-effect transistors (FETs). Although FETs built on semiconducting carbon nanotube (CNT) films have been demonstrated as promising devices for many applications, including integrated circuits (ICs), thin-film electronics, and biosensors, systemic research on the interface state of CNT film FETs, including accurate measurement and optimization schemes, is lacking. In this work, we fabricate MOS capacitors with an area of 400 μm 2 on a CNT network film with a Y 2 O 3 gate dielectric and carry out admittance measurements to investigate electrically active traps near the Y 2 O 3 /CNT interface. Through the conductance method and high-low frequency method, we extract the energy-dependent interface trap density ( D it ) and border trap density ( N bt ) of CNT MOS FETs based on the measured admittance dataset. Postdeposition annealing (PDA) processes with different gases at 300 °C show the ability to lower the D it and N bt of the Y 2 O 3 /CNT interface and then improve the performance of CNT film FETs.