journal article·2022-03-22

Impact of Annealing Temperature on Atomic Layer Deposited In–Ga–Zn–O Thin-Film Transistors

Hyun-Jun Jeong, Yoon-Seo Kim, Seok-Goo Jeong, Jin-Seong Park

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Abstract

Oxide semiconductor thin film transistors (TFTs) are promising materials for adoption in display and memory devices due to their large-area uniformity and low off-current characteristics. Because of the scaling down of devices, a uniform deposition technique is required to fabricate devices of high aspect ratio. Atomic layer deposition (ALD) is based on self-limited reaction, which enables conformal coating of high-aspect-ratio substrates. In this study, highly oriented crystalline indium–gallium–zinc oxide (IGZO) thin films and TFTs incorporating such films are fabricated by using plasma-enhanced ALD (PEALD). The postannealing process is conducted at 400–700 °C with 100 °C intervals. As the annealing temperature increases, the device performances and reliability gradually degrade. High density and highly ordered crystalline IGZO thin films are obtained at high annealing temperature. However, the device characteristics using such films are degraded due to the dramatically reduced hydrogen content in the oxide semiconductor at high annealing temperature. This study shows that highly ordered IGZO thin films can be deposited by ALD. If the process used to fabricate highly ordered IGZO thin films could retain moderate hydrogen content, it would be possible to manufacture oxide TFTs with excellent electrical performances.
Source: openalex_inverted_index · Quality: baseline

Research context

OpenAlex topics: Thin-Film Transistor Technologies · Semiconductor materials and devices · ZnO doping and properties

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

Affiliations

Division of Materials Science and Engineering, Hanyang University, 222 Wangsimni-ro, Seongdong-gu, Seoul 04763, Republic of Korea

R&D Center, Samsung Display, 95 Samsung 2-ro, Giheung-gu, Yongin-si 17113, Republic of Korea

Division of Nanoscale Semiconductor Engineering, Hanyang University, 222 Wangsimni-ro, Seongdong-gu, Seoul 04763, Republic of Korea

Funding

Ministry of Trade, Industry and Energy

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