Optimal design of a novel amorphous silicon gate driver circuit using a TFT-circuit-simulation-based multi-objective evolutionary algorithm

ABSTRACTA short rise time, short fall time, and small ripple are required to reduce the misoperation of pixel data voltage and to improve the stable signal processing of a driver circuit. In this study, a novel amorphous silicon gate (ASG) driver circuit consisting of 15 hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) and two capacitors was optimized using a thin-film transistor (TFT)-circuit-simulation-based multi-objective evolutionary algorithm on the unified optimization framework . The ASG circuit was optimized for the following given specifications: rise time <0.7 µs; fall time <0.6 µs; ripple peak <6.5 V; clock Ctotal <40 pf; and total TFT widths <6000 µm. The main findings of this study show that the rise time had an 18% reduction and that the fall time, total widths, and clock Ctotal had 7, 17.5, and 9% reductions, respectively.