Design and Comparative Analysis of Gate Stack Silicon Doped HfO2 Ferroelectric Vertical TFET

In this work, a gate stack Silicon doped HfO2 ferroelectric vertical TFET is proposed and its various performance parameters are investigated and compared with the high-K HfO2 vertical TFET and SiO2 vertical TFET with embedded SiGe layer at the source channel Junction to reduce tunneling band gap from 1.1 eV to 0.7 eV. The optimized proportion of the Si to retain the polarization is 3.4% chosen to build the Silicon doped HfO2 ferroelectric. The introduction of a gate stack Silicon doped HfO2 ferroelectric with the HfO2 causes two major phenomena, in first it reduces the surface potential in the off state of the device and prohibited the electron tunneling from the source and hence results in very low off state current. In second, its setup negative gate capacitance and hence increases the overall gate capacitance coupling to ensure high drain current and the low subthreshold slope of the device and thus provide a high switching speed. It is seen that using a gate stack Silicon doped HfO2 ferroelectric, the off current is 2 orders lowers as compared to the HfO2 and 3 orders lower as compared to the SiO2. Also, the proposed device gives subthreshold slope of 14.37 mV/ Dec which is a significant improvement as compared to the HfO2 and SiO2 bases vertical TFET. The highest ON/OFF current ratio is reported to be in the order of 10~13 respectively.