A Novel Metal Dielectric Metal Based GAA-Junction-Less TFET Structure for Low Loss SRAM Design

This paper investigates the performance of the gate all around junction-less tunnel field effect transistor (GAA-JLTFET) device with Metal-dielectric-metal–insulator-semiconductor (MDMIS) configuration for low leakage SRAM design. The proposed device structure (MDMIS-GAA-JLTFET) effectively suppresses the subthreshold swing (SS) of the transistor and produces a lower SS of 15 mV/decade. The use of high-k dielectric layer generates a high on current of 1.69 mA/µm, and supress an off current up to 10–18 A/µm which results due to blocking of source tunnelling current in the off-state. The effect of high-k dielectric is optimized using ATLAS tool to make sure that the proposed device structure is capable for low leakage SRAM design. The use of high-k material as an insulator in MDMIS structure assured it to be used in low leakage memory system. The promising capability of proposed structure makes the 6 T- SRAM cell structure lossless. Further, the simulated SRAM cell is compared with CMOS based SRAM which ensures that’s the proposed MDMIS based SRAM is suitable for low leakage memory system.