Back Bias Induced Modeling of Subthreshold Characteristics of SOI Junctionless Field Effect Transistor (JLFET)
Source abstract
Abstract
In the present article, the modeling of subthreshold current of asymmetric silicon-on-insulator (SOI) Junctionless Field Effect Transistors (JLFETs) is done. The switching properties are further investigated by formulating the subthreshold swing characteristics based on the minimum potential concept. The model adopts the effect of substrate-induced surface potential (SISP) effect as well as source/drain depletion region with necessary changes in the boundary conditions at the silicon-buried oxide (BOX) interface. The developed model is beneficial for the optimization of low power switching characteristics for SOI JLFETs. The model results are validated with the numerical simulation results obtained from Sentaurus TCAD simulator.
Source: openaire · Quality: candidate unverified · Source record ↗
Research context
OpenAlex topics: Advancements in Semiconductor Devices and Circuit Design · Integrated Circuits and Semiconductor Failure Analysis · Semiconductor materials and devices
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References (21)
Show source-provided references
1. Huaxiang Y, Jiaxin Y (2018). Advanced transistor process technology from 22- to 14-nm node, Complementary Metal Oxide Semiconductor, Kim Ho Yeap and Humaira Nisar, IntechOpen, DOI: https://doi.org/10.5772/intechopen.7865510.5772/intechopen.78655 ↗
2. Colinge J, Lee C, Afzalian A et al (2010) Nanowire transistors without junctions. Nature Nanotech 5:225–22910.1038/nnano.2010.15 ↗
3. Rassekh A, Fathipour M (2020) A single-gate SOI nanosheet Junctionless transistor at 10-nm gate length: design guidelines and comparison with the conventional SOI FinFET. J Comput Electron 19:631–639. https://doi.org/10.1007/s10825-020-01475-910.1007/s10825-020-01475-9 ↗
4. Celler GK (2003) Frontiers of silicon-on-insulator. J Appl Phy 93:4955–497810.1063/1.1558223 ↗
5. Gola D, Singh B, Tiwari PK (2017) A threshold voltage model of tri-gate junctionless field-effect transistors including substrate bias effects. IEEE Trans Elec Dev 64:3534–354010.1109/TED.2017.2722044 ↗
6. Singh B, Gola D, Singh K, Goel E, Kumar S, Jit S (2016) Analytical modeling of channel potential and threshold voltage of double-gate junctionless FETs with a vertical Gaussian-like doping profile. IEEE Trans Elec Dev 63:2299–230510.1109/TED.2016.2556227 ↗
7. Jiang C, Liang R, Wang J, Xu J (2015) A two-dimensional analytical model for short channel junctionless double-gate MOSFETs. AIP Adv 5:57122–1–57122–57122–1–57113
8. Woo J-H, Choi J-M, Choi Y-K (2013) Analytical threshold voltage model of junctionless double-gate MOSFETs with localized charges. IEEE Trans Elec Dev 60:2951–295510.1109/TED.2013.2273223 ↗
9. Kumar A, Tiwari PK (2014) A threshold voltage model of short channel fully-depleted recessed-source/drain (re-S/D) UTB SOI MOSFETs including substrate induced surface potential effects. Solid State Electron 95:52–6010.1016/j.sse.2014.03.004 ↗
10. Dixit VK, Gupta R, Purwar V, Srinivas PSTN, Dubey S (2020) Effect of substrate induced surface potential (SISP) on threshold voltage of SOI junction-less field effect transistor (JLFET). Silicon (Springer) 12:921–92610.1007/s12633-019-00185-7 ↗
11. Chiang T-K (2012) A quasi-two-dimensional threshold voltage model for short-channel junctionless double-gate MOSFETs. IEEE Trans Elec Dev 59:2284–228910.1109/TED.2012.2202119 ↗
12. Baruah RK (2015). Modelling and simulation of short channel Junctionalless Transistor from an Analog Design Perspective. PhD Thesis, Indian Institute of Technology, Guwahati, Assam, India
13. Woo J-H, Choi J-M, Choi Y-K (2013) Analytical threshold voltage model of Junctionless double-gate MOSFETs with localized charges. IEEE trans. Elec Dev 60:2951–295510.1109/TED.2013.2273223 ↗
14. Sim J-H, Kuo J-B (1993) An analytical back-gate bias effect model for ultrathin SOI CMOS devices. IEEE trans. Elec Dev 40:755–76510.1109/16.202788 ↗
15. Fjeldly TA, Shur M (1993) Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFETs. IEEE Trans Elec Dev 40:137–14510.1109/16.249436 ↗
16. Taur Y, Ning TH (2009) Fundamentals of modern VLSI devices2nd edn. Cambridge Univ Press, UK10.1017/CBO9781139195065 ↗
17. Gnudi A, Reggiani S, Gnani E, Baccarani G (2013) Semi-analytical model of the subthreshold current in short-channel Junctionless symmetric double-gate field-effect transistors. IEEE Trans Elec Dev 60:1342–134810.1109/TED.2013.2247765 ↗
18. Gola D, Singh B, Tiwari PK (2018) Subthreshold modeling of tri-gate Junctionless transistors with variable channel edges and substrate bias effects. IEEE Trans Elec Dev 65:1663–167110.1109/TED.2018.2809865 ↗
19. Synopsys (2016). Sentaurus device user guide, version N-2017, 09. Mountain View CA USA
20. Omura Y, Horiguchi S, Tabe M, Kishi K (1993) Quantum mechanical effects on the threshold voltage of ultrathin-SOI NMOSFETs. IEEE Electron Device Lett 14:569–57110.1109/55.260792 ↗
21. Colinge JP, Kranti A, Yan R, Lee CW, Ferain I, Yu R, Dehdashti Akhavan N, Razavi P (2011) Junctionless nanowire transistor (JNT): properties and design guidelines. Solid State Electron 65–66:33–3710.1016/j.sse.2011.06.004 ↗