journal article·2022-12

Analytical Model and Mechanism of a Linear Extended Gate for Lateral Internal Superjunction Power Devices

Lijuan Wu, Jinsheng Zeng, Xing Chen, Haifeng Wu, Shaolian Su

Silicon· Volume 14· Issue 18
Publisher page

Abstract

The analytical model and mechanism of a linear extended gate (LEG) for internal superjunction lateral double-diffused metal-oxide semiconductor (LEG-ISJ LDMOS) is developed in this paper. The LEG-ISJ structure features a LEG structure on the top of the device that connects two back-to-back diodes on the right. An accumulation layer with high electron density can be formed by the LEG to increase the drift region current density in the ON-state. Besides, the surface electric field of the LEG is modulated by semiconductor insulator semiconductor (SIS) structure in the OFF-state. Meanwhile, the superjunction below the drift region introduces a new current conduction path. The current of the LEG-ISJ is obtained by solving the Current density’s equation. The simulation results are in good agreement with the analytical model. An extremely low specific ON-resistance (RON,sp) of 5.88 mΩ·cm2 and a high breakdown voltage (BV) of 416 V are realized. Therefore, an extremely high FOM = BV2/RON,sp of 29.43 MW/cm2 is obtained for the LEG-ISJ LDMOS.
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Research context

OpenAlex topics: HVDC Systems and Fault Protection · Superconducting Materials and Applications · Silicon Carbide Semiconductor Technologies

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References (26)

Show source-provided references
1. Fujihira T, Miyasaka Y (2002) Simulated superior performances of semiconductor superjunction devices, in Proc 10th Int Symp. Power Semicond. Devices (IISPSD), Kyoto, Japan, pp 423–426
2. Baliga BJ (2008) Fundamentals of power semiconductor devices. Springer, New York, NY, USA10.1007/978-0-387-47314-7 ↗
3. Chen XB (1993) Semiconductor power devices with alternating conductivity. U.S. Patent 5 216 275
4. Chen XB, Mawby PA, Board K, Salama CAT (1998) Theory of a novel voltage-sustaining layer for power devices. Microelectron J 29(12):1005–101110.1016/S0026-2692(98)00065-2 ↗
5. Strollo AGM, Napoli E (2001) Optimal ON-resistance versus breakdown voltage tradeoff in superjunction power devices: a novel analytical model. IEEE Trans. Electron Devices 48(9):2161–216710.1109/16.944211 ↗
6. Huang H, Chen X (2013) Optimization of specifific on-resistance of semisuperjunction trench MOSFETs with charge balance. IEEE Trans Electron Devices 60(3):1195–120110.1109/TED.2013.2242331 ↗
7. Chen X, Sin JKO (2001) Optimization of the specifific on-resistance of the COOLMOS. IEEE Trans Electron Devices 48(2):344–34810.1109/16.902737 ↗
8. Nassif-Khalil SG, Salama CAT (2002) Super junction LDMOST in silicon-on-sapphire technology (SJ-LDMOST). Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics, pp. 81–84
9. Nassif-Khalil SG, Salama CAT (2003) Super-junction LDMOST on a silicon-on-sapphire substrate. IEEE Trans Electron Devices 50(5):1385–139110.1109/TED.2003.813460 ↗
10. Honarkhah S, Nassif-Khalil S, Salama CAT (2004) Back-etched super-junction LDMOST on SOI. Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850), pp. 117–12010.1109/ESSDER.2004.1356502 ↗
11. Zhang B, Zhang W, Li Z, Qiao M, Li Z (2014) Equivalent substrate model for lateral super junction device. IEEE Trans Electron Devices 61(2):525–53210.1109/TED.2013.2295091 ↗
12. Zhang W, Zhang B, Li Z, Qiao M, Li Z (2015) Theory of Superjunction with NFD and FD modes based on normalized breakdown voltage. IEEE Trans Electron Devices 62(12):4114–412010.1109/TED.2015.2491360 ↗
13. Ppt A, Ying WB, Fei CB et al (2019) Super junction LDMOS with P-trench and stepped buried oxide layer for high performance - ScienceDirect[J]. Superlattice Microst 125:198–20410.1016/j.spmi.2018.11.005 ↗
14. Sze SM, Lee M-K (2012) Semiconductor devices: physics and technology. Wiley, Hoboken, NJ, USA
15. Caughey DM, Thomas RE (1967) Carrier mobilities in silicon empirically related to doping and field. Proc IEEE 55(12):2192–219310.1109/PROC.1967.6123 ↗
16. Sun SC, Plummer JD (1980) Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces. IEEE J Solid State Circuits 15(4):562–57310.1109/JSSC.1980.1051439 ↗
17. Lin M J, Lee T H, Chang F L, et al. Lateral Superjunction Reduced Surface Field Structure for the Optimization of Breakdown and Conduction Characteristics in a High-Voltage Lateral Double Diffused Metal Oxide Field Effect Transistor[J]. Jpn J Appl Phys, 2014, 42(Part 1, No. 12):7227–723110.1143/JJAP.42.7227 ↗
18. Duan B, Yang Y, Zhang B (2009) New superjunction LDMOS with Ntype charges’ compensation layer. IEEE Electron Device Lett 30(3):305–30710.1109/LED.2009.2012396 ↗
19. Duan BX, Cao Z, Yuan XN, Yuan S, Yang YT (2015) New superjunction LDMOS breaking silicon limit by electric fifield modulation of buffered step doping. IEEE Electron Device Lett 36(1):47–4910.1109/LED.2014.2366298 ↗
20. Zhang B, Chen L, Wu J, Li Z (2005) SLOP-LDMOS-a novel superjunction concept LDMOS and its experimental demonstration. In Proc. Int. Conf. Commun., Circuits Syst., pp. 1399–1402
21. Zhang W et al. (2018) Non-full depletion mode and its experimental realization of the lateral superjunction. 2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp. 475–47810.1109/ISPSD.2018.8393706 ↗
22. Zhang W, He J, Cheng S, Zhang S, He B, Qiao M, Li Z, Zhang B (2020) Novel self-modulated lateral Superjunction device suppressing the inherent 3-D JFET effect. IEEE Electron Device Lett 41(9):1392–139510.1109/LED.2020.3009994 ↗
23. Deng G, Luo X, Zhao Z, Wei J, Cheng S, Li C, Ma Z, Zhang B, Zhang S (2020) Experimental study of 600 V accumulation-type lateral double-diffused MOSFET with ultra-low on-resistance. IEEE Electron Device Lett 41(3):465–46810.1109/LED.2020.2970006 ↗
24. Wei J et al. (2015) Accumulation-mode high voltage SOI LDMOS with ultralow specific on-resistance. 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD), pp. 185–18810.1109/ISPSD.2015.7123420 ↗
25. Iqbal MM, Udrea F, Napoli E (2009) On the static performance of the RESURF LDMOSFETS for power ICs. 2009 21st International Symposium on Power Semiconductor Devices & IC's, pp. 247–25010.1109/ISPSD.2009.5158048 ↗
26. Lyu X, Chen X (2013) An ultralow specifific on-resistance LDMOST using charge balance by split p-gate and n-drift regions. IEEE Trans Electron Devices 60(11):3821–382610.1109/TED.2013.2283426 ↗