Deep Insight into the Noise Behavior of SiGe Source Based Epitaxial Layer Tunnel Field Effect Transistor
Source abstract
Abstract
A detailed simulation-based investigation on the noise behavior of SiGe source-based Epitaxial layer Tunnel field effect transistor (SiGe source ETLTFET) and Silicon Synthetic Electric field TFET (Si-SETFET) in the presence of interface trap charges having Gaussian distribution is presented in this paper. The results demonstrated that the flicker and G-R noises dominate the noise characteristics at low frequencies, while diffusion noise is the major contributor at high frequencies for both devices. The drain current noise spectral density (Sid) behavior of SiGe source ETLTFET in the presence of trap shows a reduced value than Si-SETFET. The preceding argument is supported by the observation of normalised Sid (Sid/IDS2) vs Drain current (IDS). The value of net Sid for SiGe source ETLTFET is found to be ~10−26 A2/Hz till 1 MHz. Furthermore, noise analysis at various temperatures shows that noise in presence of trap charges has a greater influence at lower temperatures in the higher drain current region. The result also revealed that the the Sid vs. frequency variation is a decreasing function of the Ge mole fraction in SiGe source ETLTFET. A brief comparison of net Sid among some of the reported studies and this study has also been presented. SiGe source ETLTFET is found to be more noise immune over a wider frequency range in comparison to the state of the art devices.
Source: expertdata · Quality: candidate unverified · Source record ↗
Research context
OpenAlex topics: Advancements in Semiconductor Devices and Circuit Design · Integrated Circuits and Semiconductor Failure Analysis · Semiconductor materials and devices
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
References (51)
Show source-provided references
1. Knoch J, Avouris P (2004) Tunneling versus thermionic emission in one-dimensional semiconductors. Phys Rev Lett 92:2–5. https://doi.org/10.1103/PhysRevLett.92.04830110.1103/PhysRevLett.92.048301 ↗
2. Vandenberghe WG, Verhulst AS, Sorée B et al (2013) Figure of merit for and identification of sub-60 mV/decade devices. Appl Phys Lett 102:57–61. https://doi.org/10.1063/1.477352110.1063/1.4773521 ↗
3. Seabaugh AC, Zhang Q (2010) Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE 98:2095–2110. https://doi.org/10.1109/JPROC.2010.207047010.1109/JPROC.2010.2070470 ↗
4. Hemanjaneyulu K, Shrivastava M (2015) Fin enabled area scaled tunnel FET. IEEE Trans Electron Devices 62:3184–3191. https://doi.org/10.1109/TED.2015.246967810.1109/TED.2015.2469678 ↗
5. Park W, Hanna AN, Kutbee AT, Hussain MM (2018) In-line tunnel field effect transistor: drive current improvement. IEEE J Electron Devices Soc 6:721–725. https://doi.org/10.1109/JEDS.2018.284402310.1109/JEDS.2018.2844023 ↗
6. Yang Z (2016) Tunnel field-effect transistor with an L-shaped gate. IEEE Electron Device Lett 37:839–842. https://doi.org/10.1109/LED.2016.257482110.1109/LED.2016.2574821 ↗
7. Morita Y, Mori T, Migita S et al (2014) Performance enhancement of tunnel field-effect transistors by synthetic electric field effect. IEEE Electron Device Lett 35:792–79410.1109/LED.2014.2323337 ↗
8. Lee JW, Choi WY (2017) Triple-gate tunnel FETs encapsulated with an epitaxial layer for high current drivability. J Semicond Technol Sci 17:271–276. https://doi.org/10.5573/JSTS.2017.17.2.27110.5573/JSTS.2017.17.2.271 ↗
9. Debnath RG, Baishya S (2022) Variability analysis of the epitaxial layer TFET due to gate work function variation, random dopant fluctuation, and oxide thickness fluctuation using the statistical impedance field method. Semicond Sci Technol:1–9. https://doi.org/10.1088/1361-6641/ac65a8 Manuscript10.1088/1361-6641/ac65a8 ↗
10. Panchanan S, Maity R, Baishya S, Maity NP (2021) Modeling, simulation and analysis of surface potential and threshold voltage: application to high-K material HfO2 based FinFET. Silicon 13:3271–3289. https://doi.org/10.1007/s12633-020-00607-x10.1007/s12633-020-00607-x ↗
11. Chakrabarti H, Maity R, Baishya S, Maity NP (2022) An accurate model of threshold voltage and effect of high-K material for fully depleted graded channel DMDG MOSFET. Silicon. https://doi.org/10.1007/s12633-021-01412-w10.1007/s12633-021-01412-w ↗
12. Maity NP, Maity R, Thapa RK, Baishya S (2014) Study of interface charge densities for ZrO2 and HfO2 based metal-oxide-semiconductor devices. Adv Mater Sci Eng:1–6. https://doi.org/10.1155/2014/49727410.1155/2014/497274 ↗
13. Maity NP, Thakur RR, Maity R et al (2016) Analysis of interface charge densities for high-k dielectric materials based metal oxide semiconductor devices. Int J Nanosci 15(1660011):1–6. https://doi.org/10.1142/S0219581X1660011510.1142/S0219581X16600115 ↗
14. Chander S, Sinha SK, Chaudhary R (2021) Comprehensive review on electrical noise analysis of TFET structures. Superlattice Microst. https://doi.org/10.1016/j.spmi.2021.10710110.1016/j.spmi.2021.107101 ↗
15. Debnath RG, Baishya S (2022) Impact of interface trap charge and temperature on the performance of epitaxial layer tunnel field effect transistor. Microelectron J 120:1–8. https://doi.org/10.1016/j.mejo.2021.10534810.1016/j.mejo.2021.105348 ↗
16. Hooge FN (1994) L / f noise sources. IEEE Trans electron devices 41:1926–193510.1109/16.333808 ↗
17. Song H, Lim D, Kwon S et al (2018) Low frequency noise of silicon based tunneling field effect transistors. International Conference on Electronics, Information and Communication, ICEIC. pp 2–3. https://doi.org/10.23919/ELINFOCOM.2018.833067910.23919/ELINFOCOM.2018.8330679 ↗
18. Knitel MJ, Woerlee PH, Scholten AJ, Zegers-Van Duijnhoven ATA (2000) Impact of process scaling on 1/f noise in advanced CMOS technologies. International Electron Devices Meeting (IEDM), pp 463–466
19. Huang Q, Huang R, Chen C et al (2014) Deep insights into low frequency noise behavior of tunnel FETs with source junction engineering. Dig Tech Pap Symp VLSI Technol:7–8. https://doi.org/10.1109/VLSIT.2014.689437110.1109/VLSIT.2014.6894371 ↗
20. Mohata DK, Liu H, Datta S (2012) Flicker noise characterization and analytical modeling of Homo and Hetero-Junction III-V Tunnel FETs. 70th Device Research Conference. pp 203–204. https://doi.org/10.1109/DRC.2012.625703210.1109/DRC.2012.6257032 ↗
21. Chander S, Sinha SK, Chaudhary R (2022) Comprehensive review on electrical noise analysis of TFET structures. Superlattice Microst 161:107101. https://doi.org/10.1016/j.spmi.2021.10710110.1016/j.spmi.2021.107101 ↗
22. Fan ML, Hu VPH, Chen YN, et al (2011) Impacts of single trap induced random telegraph noise on finfet devices and SRAM cell stability. Proc - IEEE Int SOI Conf 1–2. https://doi.org/10.1109/SOI.2011.608167610.1109/SOI.2011.6081676 ↗
23. Das B, Bhowmick B (2020) Noise behavior of ferro electric tunnel FET. Microelectron J 96:104677. https://doi.org/10.1016/j.mejo.2019.10467710.1016/j.mejo.2019.104677 ↗
24. Goswami R, Bhowmick B, Baishya S (2016) Effect of scaling on noise in circular gate TFET and its application as a digital inverter. Microelectron J 53:16–24. https://doi.org/10.1016/j.mejo.2016.04.00910.1016/j.mejo.2016.04.009 ↗
25. Hung KK, Ko PK, Hu C, Cheng YC (1990) A physics-based MOSFET noise model for circuit simulators. IEEE Trans Electron Devices 37:1323–1333. https://doi.org/10.1109/16.10819510.1109/16.108195 ↗
26. Neves FS, Agopian PGD, Martino JA et al (2016) Low-frequency noise analysis and modeling in vertical tunnel FETs with Ge source. IEEE Trans Electron Devices 63:1658–1665. https://doi.org/10.1109/TED.2016.253336010.1109/TED.2016.2533360 ↗
27. Pandey R, Rajamohanan B, Liu H et al (2014) Electrical noise in heterojunction interband tunnel FETs. IEEE Trans Electron Devices 61:552–560. https://doi.org/10.1109/TED.2013.229349710.1109/TED.2013.2293497 ↗
28. Cao W, Yao CJ, Jiao GF et al (2011) Improvement in reliability of tunneling field-effect transistor with p-n-i-n structure. IEEE Trans Electron Devices 58:2122–2126. https://doi.org/10.1109/TED.2011.214498710.1109/TED.2011.2144987 ↗
29. Huang R, Huang Q, Zhao Y et al (2017) New steep-slope device of comprehensive properties enhancement with hybrid operation mechanism for ultra-low-power applications. 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference (S3S). pp 1–3. https://doi.org/10.1109/S3S.2017.830875510.1109/S3S.2017.8308755 ↗
30. Balandin AA (2013) Low-frequency 1/f noise in graphene devices. Nat Nanotechnol 8:549–555. https://doi.org/10.1038/nnano.2013.14410.1038/nnano.2013.144 ↗
31. Li G, Kilchytska V, Andre N et al (2017) Leakage current and low-frequency noise analysis and reduction in a suspended SOI lateral p-i-n diode. IEEE Trans Electron Devices 64:4252–4259. https://doi.org/10.1109/TED.2017.274286310.1109/TED.2017.2742863 ↗
32. Bu ST, Huang DM, Jiao GF et al (2017) Low frequency noise in tunneling field effect transistors. Solid State Electron 137:95–101. https://doi.org/10.1016/j.sse.2017.08.00810.1016/j.sse.2017.08.008 ↗
33. Van Der Wel AP, Klumperink EAM, Kolhatkar JS (2007) Low-frequency noise phenomena in switched MOSFETs. IEEE J Solid State Circuits 42:540–549. https://doi.org/10.1109/JSSC.2006.89171410.1109/JSSC.2006.891714 ↗
34. Xu J, Deen MJ (2002) MOSFET 1/f noise model based on mobility fluctuation in linear region. Electron Lett 38:1–2. https://doi.org/10.1049/el:2002028210.1049/el:20020282 ↗
35. Bijesh R, Mohata DK, Liu H, Datta S (2012) Flicker noise characterization and analytical modeling of homo and hetero-junction III-V tunnel FETs. 70th Device Res Conf 37:203–204. https://doi.org/10.1109/DRC.2012.625703210.1109/DRC.2012.6257032 ↗
36. Sentaurus (2017) Sentaurus device user guide. Synopsys, Mountain View, CA, USA, 2017
37. Vandooren A, Leonelli D, Rooyackers R et al (2013) Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction tunnel-FETs. Solid State Electron 83:50–55. https://doi.org/10.1016/j.sse.2013.01.02610.1016/j.sse.2013.01.026 ↗
38. Schenk A (1992) A model for the field and temperature dependance of Shockley-read-hall lifetimes in silicon. Solid State Electron 35:1585–159610.1016/0038-1101(92)90184-E ↗
39. Hellings G, Eneman G, Krom R et al (2010) Electrical TCAD simulations of a germanium pMOSFET technology. IEEE Trans Electron Devices 57:2539–2546. https://doi.org/10.1109/TED.2010.206072610.1109/TED.2010.2060726 ↗
40. Ionescu AM, Riel H (2011) Tunnel field effect transistor as energy-efficient electronic switches. Nature 479:329–337. https://doi.org/10.1038/nature1067910.1038/nature10679 ↗
41. von Haartman M, Östling M (2007) Low frequency noise in advanced MOS devices. Springer, Dordrecht, Netherlands10.1007/978-1-4020-5910-0 ↗
42. Nougier J (1994) Fluctuations and noise of hot carriers in semiconductor materials and devices. IEEE Trans electron devices 41:2034–204910.1109/16.333821 ↗
43. Goswami R, Bhowmick B, Baishya S (2015) Electrical noise in circular gate tunnel FET in presence of interface traps. Superlattice Microst 86:342–354. https://doi.org/10.1016/j.spmi.2015.07.06410.1016/j.spmi.2015.07.064 ↗
44. Burstein E, Kingston RH, McWhorter AL (1957) Semiconductor Surface Physics. University of Pennsylvania Press, Philadelphia (Pa.)
45. Ghibaudo G, Boutchacha T (2002) Electrical noise and RTS fluctuations in advanced CMOS devices. Microelectron Reliab 42:573–582. https://doi.org/10.1016/S0026-2714(02)00025-210.1016/S0026-2714(02)00025-2 ↗
46. Talukdar J, Rawat G, Singh K, Mummaneni K (2021) Low frequency noise analysis of single gate extended source tunnel FET. Silicon 13:3971–3980. https://doi.org/10.1007/s12633-020-00712-x10.1007/s12633-020-00712-x ↗
47. Chander S, Sinha SK, Kumar S et al (2017) Temperature analysis of Ge/Si heterojunction SOI-tunnel FET. Superlattice Microst 110:162–170. https://doi.org/10.1016/j.spmi.2017.08.04810.1016/j.spmi.2017.08.048 ↗
48. Hellenbrand M, Memiševi E, Berg M et al (2017) Low-frequency noise in III – V nanowire TFETs and MOSFETs. IEEE Electron Device Lett 38:1520–152310.1109/LED.2017.2757538 ↗
49. Wangkheirakpam VD, Bhowmick B, Pukhrambam PD (2021) Noise behavior of vertical tunnel FETs under the influence of interface trap states noise behavior of vertical tunnel FETs under the in fluence of interface trap states. Microelectron J 114. https://doi.org/10.1016/j.mejo.2021.10512410.1016/j.mejo.2021.105124 ↗
50. Wangkheirakpam VD, Bhowmick B, Pukhrambam PD (2020) Investigation of N+ pocket-doped junctionless vertical TFET and its digital inverter application in the presence of true noises. Appl Phys A Mater Sci Process 126:1–10. https://doi.org/10.1007/s00339-020-03983-810.1007/s00339-020-03983-8 ↗
51. Ghosh P, Bhowmick B (2020) Noise behaviour of δp+ Si1−xGex layer SELBOX TFET. Indian J Phys 94:493–500. https://doi.org/10.1007/s12648-019-01485-910.1007/s12648-019-01485-9 ↗