Structural Process Variation on Silicon Nanotube Tunnel Field-Effect Transistor
Source abstract
Abstract
In this manuscript, we have investigated the geometrical process variation of a 3-dimensinal silicon nanotube tunnel field effect transistor (Silicon NT-TFET) using TCAD numerical simulations. The device tube wall thickness and gate length have been tuned to investigate the effects on silicon NT-TFET performance. The performance indicators for silicon-NT-TFETs are ON current, OFF current, transconductance (gm), sub-threshold slope (SS), output resistance (ro) and unity gain cut off frequency (ft), and also analyzed the sensitivity of the silicon NT-TFET performance metrics for various silicon tube wall thicknesses such as IOFF, ION, gm and ft. A Silicon NT-TFET provides better performance with a thicker tube wall thickness and shorter gate length.
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Research context
OpenAlex topics: Advancements in Semiconductor Devices and Circuit Design · Semiconductor materials and devices · Integrated Circuits and Semiconductor Failure Analysis
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