Analog/RF Performance Projection of Ultra-Steep Si Doped HfO2 Based Negative Capacitance Electrostatically Doped TFET: A Process Variation Resistant Design

The incorporation of Si doped HfO2 in negative capacitance electrostatically doped TFET realizes ultra-steep and process variation resistant structure. Here, Si:HfO2 is the gate stack ferroelectric material is used in conjunction with a high-K gate dielectric HfO2/TiO2. The conceptualization of intrinsic gate voltage amplification due to the alignment of ferroelectric dipoles comprehends the negative capacitance (NC) behavior. Moreover, the work-function difference between the source/drain electrodes and the silicon induces electrostatic doping. Thus, the detrimental doping related issues, heavy doping governed mobility degradation and statistical random dopant fluctuations (RDFs) can be eliminated and it results in more process variations immune design. This work has explored the impact of the symmetric and asymmetric structure of the considered devices on both the drain and source sides, in terms of the oxide thickness between the electrodes and the Si body. Here, analog/RF performance estimation is also carried out for the parameters such as transconductance (gm), output conductance (gd), unity gain frequency (fT), intrinsic gain (AV), transconductance frequency product (TFP), and gain frequency product (GFP), etc. Our study reveals that Si:HfO2 ferroelectric gate stack with TiO2 dielectric shows better device performance than Si:HfO2 ferroelectric gate stack with HfO2 dielectric for both dc as well as ac performance.