journal article·2022-08

Improved Switching Performance of a Novel Auxiliary Gate Raised Dual Material Hetero-Dielectric Double Gate Tunnel Field Effect Transistor

Brahmdutta Dixit, Reshmi Maity, N. P. Maity

Silicon· Volume 14· Issue 12
Publisher page

Abstract

This paper suggested auxiliary gate raised dual material hetero-dielectric double-gate- tunnel-field-effect-transistor (DGTFET). The recommended device provides greater ON-state current (ION), larger ON/OFF current and lesser sub-threshold swing compared to conventional single material hetero-dielectric DGTFET. The raised gate at the drain terminal as well as use of dual material of the proposed DGTFET provides better performances by decreasing the tunneling barrier size on source channel junction for which band to band tunneling (BTBT) increases which in turns improves the ON-state current. The suggested device is found to have a higher ON/OFF ratio about 1012 and subthreshold swing (SS) of 35 mV/dec in comparison to the conventional device.
Source: openaire · Quality: candidate unverified · Source record ↗

Research context

OpenAlex topics: Semiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Ferroelectric and Negative Capacitance Devices

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

References (33)

Show source-provided references
1. Hu, C.: Green transistor as a solution to the IC power crisis. In: Proc. IEEE 9th Int. Conf. Solid-State Integr.-Circuit Technol.,pp. 16–20 (Oct. 2008)10.1109/ICSICT.2008.4735116 ↗
2. Kumar M, Jit S (2015) A novel four-terminal ferroelectric tunnel FET for quasi-ideal switch. IEEE Trans. Nanotechnol. 14(4):600–60210.1109/TNANO.2015.2427195 ↗
3. Kumar M, Jit S (2015) Ëffects of electrostatically doped source/drain and ferroelectric gate oxide on subthreshold swing and impact ionization rate of strained-Si-on-insulator tunnel field-effect transistors. IEEE Trans. Nanotechnol. 14(4):597–59910.1109/TNANO.2015.2426316 ↗
4. Saurabh S, Kumar MJ (2013) Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Trans. Electron Devices 60(10):3285–329010.1109/TED.2013.2276888 ↗
5. Gholizadeh M, Hosseini SE (2014) A 2-D analytical model for double-gate tunnel FETs. IEEE Trans. Electron Devices 61(5):1494–150010.1109/TED.2014.2313037 ↗
6. Bhuwalka KK, Schulze J, Eisele I (2015) Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering. IEEE Trans. Electron Devices 52(5):909–91710.1109/TED.2005.846318 ↗
7. Ionescu AM, Riel H (2011) Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479:329–33710.1038/nature10679 ↗
8. Boucart K, Ionescu AM (2007) Double-gate tunnel FET with high-κ gate dielectric. IEEE Trans. Electron Devices 54(7):1725–173310.1109/TED.2007.899389 ↗
9. Kumar S, Goel E, Singh K, Singh B, Kumar M, Jit S (2016) A compact 2-D analytical model for electrical characteristics of double-gate tunnel-FETs with a SiO2/high-k stacked gate-oxide structure. IEEE Trans. Electron Devices 60:3291–329910.1109/TED.2016.2572610 ↗
10. Bagga N, Dasgupta S (2017) Surface Potential and Drain Current Analytical Model of Gate All Around Triple Metal TFETs. IEEE Trans. Electron Devices 64(2):606–61310.1109/TED.2016.2642165 ↗
11. Boucart K, Riess W, Ionescu AM (2009) Lateral strain profile as key technology booster for all-silicon tunnel FETs. IEEE Electron Devices Lett 30(6):656–65810.1109/LED.2009.2018127 ↗
12. Nayfeh OM, Ni Chleirigh C, Hennessy J, Gomez L, Hoyt JL, Antoniadis DA (2008) Design of Tunneling Field-Effect Transistors Using Strained-Silicon/strained-germanium type-II staggered heterojunctions. IEEE Electron Device Lett 29(9):1074–107710.1109/LED.2008.2000970 ↗
13. Virani HG, Adari RBR, Kottantharayil A (2010) Dual-k spacer device architecture for the improvement of performance of silicon n channel tunnel FETs. IEEE Trans. Electron Devices 57(10):2410–241710.1109/TED.2010.2057195 ↗
14. Panchanan S, Maity R, Baishya S, Maity NP (2020) Modeling, Simulation and Analysis of Surface Potential and Threshold Voltage: Application to High-K Material HfO2 Based FinFET. Silicon. https://doi.org/10.1007/s12633-020-00607-x, Published on 20th October10.1007/s12633-020-00607-x ↗
15. Kumar S, Goel E, Singh K, Chander S, Singh PK, Baral K, Singh B, Jit S (2017) 2-D analytical drain current model of double-gate heterojunction TFETs with a SiO2/high-k stacked gate oxide structure. IEEE Trans. Electron Devices 64:960–96810.1109/TED.2017.2656630 ↗
16. Saurabh S, Kumar MJ (2009) Impact of Strain on Drain Current and Threshold Voltage of Nanoscale Double Gate Tunnel Field Effect Transistor: Theoretical Investigation and Analysis. Jpn. J. Appl. Phys. 48:064503-1-710.1143/JJAP.48.064503 ↗
17. Imenabadi RM, Saremi M, Vandenberghe WG (2017) A novel PNPN-like Z-shaped tunnel field effect transistor with improved ambipolar behavior and rf performance. IEEE Trans Electron Devices 64(11):4752–475810.1109/TED.2017.2755507 ↗
18. Mallik A, Chattopadhyay A (2012) The impact of fringing field on the device performance of a pchannel tunnel field-effect transistor with a high-k gate dielectric. IEEE Trans. Elec. Dev. 59(2):277–28210.1109/TED.2011.2173937 ↗
19. Choi WY, Park B-G, Lee JD, Liu T-JK (2011) Tunneling field-effect transistors (tfets) with subthreshold swing (ss) less than 60 mv/dec. IEEE Elec. Dev. Lett. 28(8):743–74510.1109/LED.2007.901273 ↗
20. Chattopadhyay A, Mallik A (2011) Impact of a spacer dielectric and a gate overlap/underlap on the device performance of a tunnel field-effect transistor. IEEE Trans. Elec. Dev. 58(3):677–68310.1109/TED.2010.2101603 ↗
21. Koswatta S, Lundstrom M, Nikonov D (2009) Performance comparison between p-i-n tunneling transistors and conventional mosfets. Electron Devices, IEEE Trans. on Elec. Dev. 56(3):456–46510.1109/TED.2008.2011934 ↗
22. Lu, Y., Seabaugh, A., Fay, P., Koester, S.J., Laux, S., Haensch, W., Koswatta, S.O.: Geometry dependent tunnel fet performance - dilemma of electrostatics vs. quantum confinement. Device Research Conference (DRC) (2010)10.1109/DRC.2010.5551905 ↗
23. Pal A, Sachid B, Gossner H, Rao VR (2011) Insights into the design and optimization of tunnel-fet devices and circuits. IEEE Trans. Elec. Dev. 58(4):1045–105310.1109/TED.2011.2109002 ↗
24. Mallik A, Chattopadhyay A (2011) Drain-dependence of tunnel field-effect transistor characteristics: The role of the channel. IEEE Trans. Elec. Dev. 58(12):4250–425710.1109/TED.2011.2169416 ↗
25. Michielis, L.D., Lattanzio, L., Palestri, P., Selmi, L., Ionescu, A. Tunnel-fet architecture with improved performance due to enhanced gate modulation of the tunneling barrier. 69th annual device research conference (DRC) (2011)10.1109/DRC.2011.5994440 ↗
26. Panchanan S, Maity R, Baishya S, Maity NP A Surface Potential Model for Tri-Gate Metal Oxide Semiconductor Field Effect Transistor: Analysis below 10 nm Channel Length. Eng. Sci. Technol. Int. J. https://doi.org/10.1016/j.jestch.2020.12.02010.1016/j.jestch.2020.12.020 ↗
27. Chakraborty H, Maity R, Baishya S, Maity NP An Accurate Model for Threshold Voltage Analysis of Dual Material Double Gate Metal Oxide Semiconductor Field Effect Transistor. Silicon. https://doi.org/10.1007/s12633-020-00553-8 Published on 9th July, 202010.1007/s12633-020-00553-8 ↗
28. Maity NP, Maity R, Baishya S (2019) An analytical model for the surface potential and threshold voltage of a double-gate heterojunction tunnel FinFET. J. Comput. Electron. 18:65–7510.1007/s10825-018-1279-5 ↗
29. Maity NP, Maity R, Maity S, Baishya S (2019) Comparative analysis of the quantum FinFET and trigate FinFET based on modeling and simulation. J. Comput. Electron. 18:492–49910.1007/s10825-018-01294-z ↗
30. Chakrabarti H, Maity R, Kevkić Tijana, Stojanović Vladica, Maity NP (2021) Analysis of surface potential and electric field for fully depleted graded channel dual-material-double-gate MOSFET through modeling and simulation. Trans Electr Electron Mater 22(4):489–50110.1007/s42341-020-00256-2 ↗
31. Chakrabarti, H., Maity, R., and Maity, NP (2019) Analysis of surface potential for Dual-Material-Double-Gate MOSFET based on modelling and simulation. Microsyst Technol 25:4675–4684.10.1007/s00542-019-04386-3 ↗
32. Maity NP, Thakur RR, Maity R, Thapa RK, Baishya S (2016) Analysis of interface charge densities for high-k dielectric materials based metal oxide semiconductor devices. Int J Nanosci 15(05 & 06):1660011.10.1142/S0219581X16600115 ↗
33. ATLAS: 2-D Device Simulator, SILVACO Int., Santa Clara, CA, USA (2014)