Nanosheet Transistor with Inter-bridge Channels for Superior Delay Performance: A Comparative Study
Source abstract
Abstract
This paper investigates structural optimization techniques using the high-k spacer and inter-bridge Silicon (Si)-channels for superior delay performance in Silicon-based nanosheet transistors (NSHTs). NSHT devices with different channel numbers, inter-sheet distance, spacer materials, and inter-bridge channel lengths are analyzed using well-calibrated Technology Computer-Aided Design (TCAD) simulations. It is observed that the drive current improves by using high-relative permittivity (high-k) spacers in the NSHT; however, the excessive increase in gate capacitance degrades the speed performance. The study shows that using an inter-bridge channel boosts NSHT current while suppressing the gate capacitance, thus resulting in a superior delay performance compared to NSHT with high-k spacers. Reductions of 20.58%, 28.5%, and 31.7% in delay are observed for inter-bridge lengths (LIB) of 4 nm, 6 nm, and 8 nm, respectively. Compared to the NSHT with LHK = 2 nm, an improvement of 32.4% in delay for NSHT with inter-bridge channel (LIB = 8 nm), and a 12.8% degradation in delay for NSHT with high-k spacer (LHK = 12 nm) are observed.
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Research context
OpenAlex topics: Semiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Low-power high-performance VLSI design
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