Observation of Fermi level pinning at the GaAs-plasma-oxide interface

Small-signal charge transient spectroscopy (CTS) measurements of GaAs MOS diodes with plasma oxide insulating layers point to two dominant trapping levels responsible for the steady-state Fermi level pinning at the GaAs-oxide interface. The Ec-0.70 eV discrete surface trap is identified with the defect level observed in fundamental studies of III-V surfaces; this defect is due to missing As. The second level, positioned at Ec-0.67 eV' has not been reported previously. It is argued that the 0.67 eV defect is characteristic of the transition layer between the moderately doped (ND approximately 1015-1016 cm-3) GaAs substrate and the oxide.