Oxide-channel ferroelectric transistor enables ultralow-power NAND flash technology
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OpenAlex topics: Ferroelectric and Negative Capacitance Devices · Semiconductor materials and devices · Advanced Data Storage Technologies
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References (5)
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1. Micheloni R, Aritome S, Crippa L. Array architectures for 3-D NAND flash memories. Proc IEEE, 2017, 105: 1634–164910.1109/JPROC.2017.2697000 ↗
2. Kim MK, Kim IJ, Lee JS. CMOS-compatible ferroelectric NAND flash memory for high-density, low-power, and high-speed three-dimensional memory. Sci Adv, 2021, 7: eabe134110.1126/sciadv.abe1341 ↗
3. Kim IJ, Lee JS. Unlocking large memory windows and 16-level data per cell memory operations in hafnia-based ferroelectric transistors. Sci Adv, 2024, 10: eadn134510.1126/sciadv.adn1345 ↗
4. Yoo S, Kim TJ, Nam SG, et al. Ferroelectric transistors for low-power NAND flash memory. Nature, 2025, 648: 320–32610.1038/s41586-025-09793-3 ↗
5. Gong J, Ji S, Li J, et al. Three-dimensional/one-dimensional perovskite heterostructures for stable tri-state synaptic memristors. Sci China Mater, 2024, 67: 2848–285510.1007/s40843-024-2981-7 ↗