Off‐State Current Improvement of Double‐Gate Junctionless Field‐Effect Transistor by Modifying Central Potential

This work presents a double‐gate junctionless metal‐oxide field‐effect transistor (JLT) in a 20 nm regime by modifying central potential. In the proposed device, the off‐state current is reduced due to modifying the potential in the middle of the channel. The proposed structure is called as a modified central potential junctionless transistor (MCP‐JLT). The suggested device embeds two dielectric pockets (DPs) into the middle of the channel. The proposed technique has several effects on the proposed structure. Also, the impact of the DPs into the channel on the performance device is discussed. The proposed MCP‐JLT structure decreases the off‐state current (I_OFF) by three orders of magnitude; besides, it can suppress the lateral electric field and also slightly reduces the drive current (I_ON), and reduces subthreshold swing (SS) compared to a typical junctionless FET (C‐JLT). Furthermore, the effect of the gate insulator materials on the proposed device's performance is discussed.