Interface trap states induced underestimation of Schottky barrier height in metal-MX2 junctions

Understanding the interfaces between a contact metal and a two-dimensional (2D) semiconductor, as well as the dielectric gate stack and the same 2D material in transition metal dichalcogenide (TMD) based transistors, is a crucial step towards the introduction of TMD materials into advanced logic nodes. In particular, for the contact metal/2D interface, one of the key parameters is the Schottky barrier height (SBH), which is frequently extracted based on temperature-dependent subthreshold characteristics of TMD field-effect transistors (FETs). However, recently, using this methodology has resulted in rather low extracted SBH values for TMD-based transistors, which seems inconsistent with the low on-current levels in said devices. Here, we therefore connect measured device characteristics on monolayer (ML) MoS 2 transistors with technology computer-aided design (TCAD) simulations. In particular, our analysis shows that low SBHs can be incorrectly extracted when the interface trap density D it is substantial and exhibits, at the same time, a significant temperature dependence, as is the case for TMDs. In fact, TCAD simulations and comparison with the obtained electrical data reveal that the actual SBH is substantially larger than what is extracted when ignoring the above mentioned details of D it .