Tailoring the number of lines for IGO-channel 2T0C DRAM comparable to conventional 2-line operation 1T1C structure for highly scaled cell volume
Source abstract
Abstract
Abstract Capacitor-less 2T0C dynamic random-access memory (DRAM) employing oxide semiconductors (OSs) as a channel has great potential in the development of highly scaled three dimensional (3D)-structured devices. However, the use of OS and such device structures presents certain challenges, including the trade-off relationship between the field-effect mobility and stability of OSs. Conventional 4-line-based operation of the 2T0C enlarges the entire cell volume and complicates the peripheral circuit. Herein, we proposed an IGO (In-Ga-O) channel 2-line-based 2T0C cell design and operating sequences comparable to those of the conventional Si-channel 1 T1C DRAM. IGO was adopted to achieve high thermal stability above 800 ℃, and the process conditions were optimized to simultaneously obtain a high μFE of 90.7 cm2·V−1·s−1, positive Vth of 0.34 V, superior reliability, and uniformity. The proposed 2-line-based 2T0C DRAM cell successfully exhibited multi-bit operation, with the stored voltage varying from 0 V to 1 V at 0.1 V intervals. Furthermore, for stored voltage intervals of 0.1 V and 0.5 V, the refresh time was 10 s and 1 000 s in multi-bit operation; these values were more than 150 and 15 000 times longer than those of the conventional Si channel 1T1C DRAM, respectively. A monolithic stacked 2-line-based 2T0C DRAM was fabricated, and a multi-bit operation was confirmed.
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Research context
OpenAlex topics: Semiconductor materials and devices · Low-power high-performance VLSI design · VLSI and FPGA Design Techniques
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
References (65)
Show source-provided references
1. Latency lags bandwith10.1145/1022594.1022596 ↗
2. Sparsity in deep learning: pruning and growth for efficient inference and training in neural networks10.5555/3546258.3546499 ↗
3. Checkmate: breaking the memory wall with optimal tensor rematerialization
4. Zero: memory optimizations toward training trillion parameter models
5. Roofline: an insightful visual performance model for multicore architectures10.1145/1498765.1498785 ↗
6. ADAHESSIAN: an adaptive second order optimizer for machine learning
7. AI and memory wall10.1109/MM.2024.3373763 ↗
8. The gap between processor and memory speeds
9. Future scaling of processor-memory interfaces
10. Monolithic 3-D integration10.1109/MM.2019.2942982 ↗
11. In-memory computing to break the memory wall10.1088/1674-1056/ab90e7 ↗
12. pPIM: a programmable processor-in-memory architecture with precision-scaling for deep learning10.1109/LCA.2020.3011643 ↗
13. HBM (high bandwidth memory) DRAM technology and architecture
14. DRAM refresh mechanisms, penalties, and trade-offs10.1109/TC.2015.2417540 ↗
15. Leakage power reduction in CMOS circuits using leakage control transistor technique in nanoscale technology10.47893/IJESS.2013.1113 ↗
16. Simulation for the feasibility of high-mobility channel in 3D NAND memory
17. Self-adaption of the GIDL erase promotes stacking more layers in 3D NAND flash10.3390/mi14030686 ↗
18. Impact of stacking-up and scaling-down bit cells in 3D NAND on their threshold voltages10.3390/mi13071139 ↗
19. Challenges for the DRAM cell scaling to 40nm
20. Challenges in high-aspect ratio contact (HARC) etching for DRAM capacitor formation
21. 1T-1C dynamic random access memory status, challenges, and prospects10.1109/TED.2020.2963911 ↗
22. Present status of amorphous In–Ga–Zn–O thin-film transistors10.1088/1468-6996/11/4/044305 ↗
23. Organic/inorganic hybrid buffer in InGaZnO transistors under repetitive bending stress for high electrical and mechanical stability10.1021/acsami.9b21531 ↗
24. Design of InZnSnO semiconductor alloys synthesized by supercycle atomic layer deposition and their rollable applications10.1021/acsami.9b02999 ↗
25. Resonant photoemission at the O1s threshold to characterize In2O3 single crystals10.1016/j.tsf.2013.03.036 ↗
26. High-mobility hydrogenated polycrystalline In2O3 (In2O3: h) thin-film transistors10.1038/s41467-022-28480-9 ↗
27. Scaled indium oxide transistors fabricated using atomic layer deposition10.1038/s41928-022-00718-w ↗
28. DRAM using crystalline oxide semiconductor for access transistors and not requiring refresh for more than ten days
29. Embedded memory and ARM cortex-M0 core using 60-nm C-axis aligned crystalline indium–gallium–zinc oxide FET integrated with 65-nm Si CMOS10.1109/JSSC.2016.2632303 ↗
30. Highly robust atomic layer deposition‐indium gallium zinc oxide thin‐film transistors with hybrid gate insulator fabricated via two‐step atomic layer process for high‐density integrated all‐oxide vertical complementary metal‐oxide‐semiconductor applications10.1002/sstr.202300375 ↗
31. Monolithically stacked two layers of a-IGZO-based transistors upon a-IGZO-based analog/logic circuits10.1109/TED.2023.3247364 ↗
32. 2-kbit array of 3-D monolithically-stacked IGZO FETs with low SS-64mV/dec, ultra-low-leakage, competitive μ-57 cm2/V-s performance and novel nMOS-only circuit demonstration
33. 3D-stacked CAAC-In-Ga-Zn oxide FETs with gate length of 72nm
34. First demonstration of stacked 2T0C-DRAM bit-cell constructed by two-layers of vertical channel-all-around IGZO FETs realizing 4F2 area cost
35. 1-Mbit 3-D DRAM using a monolithically stacked structure of a Si CMOS and heterogeneous IGZO FETs10.1109/JEDS.2024.3372053 ↗
36. Heterogeneous oxide semiconductor FETs comprising planar FET and vertical channel FETs monolithically stacked on Si CMOS, enabling 1-Mbit 3D DRAM
37. Capacitor-less, long-retention (>400s) DRAM cell paving the way towards low-power and high-density monolithic 3D DRAM
38. Capacitorless DRAM cells based on high-performance indium-tin-oxide transistors with record data retention and reduced write latency10.1109/LED.2022.3225263 ↗
39. Lowest IOFF < 3×10−21 A/μm in capacitorless DRAM achieved by reactive ion etch of IGZO-TFT
40. Novel vertical channel-all-around (CAA) In-Ga-Zn-O FET for 2T0C-DRAM with high density beyond 4F2 by monolithic stacking10.1109/TED.2022.3154693 ↗
41. True nonvolatile high‐speed DRAM cells using tailored ultrathin IGZO10.1002/adma.202210554 ↗
42. Improved multi-bit statistics of novel dual-gate IGZO 2T0C DRAM with In-cell VTH compensation and ΔVSN/ΔVDATA boosting technique
43. Optimized IGZO FETs for capacitorless DRAM with retention of 10 ks at RT and 7 ks at 85 °C at zero vhold with sub-10 ns speed and 3-bit operation
44. Mobility–stability trade-off in oxide thin-film transistors10.1038/s41928-021-00671-0 ↗
45. Progress, challenges, and opportunities in oxide semiconductor devices: a key building block for applications ranging from display backplanes to 3D integrated semiconductor chips10.1002/adma.202204663 ↗
46. Material characteristics and applications of transparent amorphous oxide semiconductors10.1038/asiamat.2010.5 ↗
47. Numerical analysis on effective mass and traps density dependence of electrical characteristics of a-IGZO thin-film transistors10.3390/electronics9010119 ↗
48. Device modeling of amorphous oxide semiconductor TFTs10.7567/1347-4065/ab21a5 ↗
49. Exploration of chemical composition of In–Ga–Zn–O system via PEALD technique for optimal physical and electrical properties10.1002/aelm.202201208 ↗
50. Deposition, characterization, and performance of spinel InGaZnO410.1021/acsaelm.1c01315 ↗
51. Memory characteristics of thin film transistor with catalytic metal layer induced crystallized indium-gallium-zinc-oxide (IGZO) channel10.3390/electronics11010053 ↗
52. Impact of annealing temperature on atomic layer deposited In–Ga–Zn–O thin-film transistors10.1021/acsaelm.2c00079 ↗
53. Signal margin analysis for DRAM sense amplifiers
54. Exploring innovative IGZO-channel based DRAM cell architectures and key technologies for sub-10nm node
55. High-performance thin-film transistors with an atomic-layer-deposited indium gallium oxide channel: a cation combinatorial approach10.1021/acsami.0c16325 ↗
56. c-Axis aligned 3 nm thick In2O3 crystal using new liquid DBADMIn precursor for highly scaled FET beyond the mobility–stability trade-off10.1021/acs.nanolett.3c04312 ↗
57. Unveiling the Hybrid-Channel (poly-Si/IGO) structure for 3D NAND flash memory for improving the cell current and GIDL-assisted erase operation10.1002/sstr.202400495 ↗
58. Highly C‐axis Aligned ALD‐InGaO channel improving mobility and thermal stability for next‐generation 3D memory devices10.1002/aelm.202400377 ↗
59. The impact of parasitic capacitance on the memory characteristics of 2T0C DRAM and new writing strategy10.1109/LED.2023.3287942 ↗
60. First demonstration of dual-gate IGZO 2T0C DRAM with novel read operation, one bit line in single cell, ION=1500 μA/μm@VDS=1V and retention time>300s
61. Ultrafast non‐volatile floating‐gate memory based on all‐2D materials10.1002/adma.202311652 ↗
62. Charge-selective 2D heterointerface-driven multifunctional floating gate memory for in situ sensing-memory-computing10.1021/acs.nanolett.4c03828 ↗
63. Self-selective van der Waals heterostructures for large scale memory array10.1038/s41467-019-11187-9 ↗
64. All WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration10.1038/s41467-019-13176-4 ↗
65. Monolithic 3D integration of high endurance multi-bit ferroelectric FET for accelerating compute-in-memory