Void Formation Analysis in the Molded Underfill Process for Flip-Chip Packaging

Flip-chip technology is widely used in integrated circuit (IC) packaging. Molded underfill transfer molding is the most common process for these products, as the chip and solder bumps must be protected by the encapsulating material to ensure good reliability. Flow-front merging usually occurs during the molding process, and air is then trapped under the chip, which can form voids in the molded product. The void under the chip may cause stability and reliability problems. However, the flow process is unobservable during the transfer molding process. The engineer can only check for voids in the molded product after the process is complete. Previous studies have used fluid visualization experiments and developed computational fluid dynamics simulation tools to investigate this issue. However, a critical gap remains in establishing a comprehensive three-dimensional model that integrates two-phase flow, accurate venting settings, and fluid surface tension for molded underfill void evaluation—validated by experimental fluid visualization. This study aims to address this gap in the existing literature. In this study, a fluid visualization experiment was designed to simulate the transfer molding process, allowing for the observation of flow-front merging and void formation behaviors. For comparison, a three-dimensional mold flow analysis was also performed. It was found that the numerical simulation of the trapped air compression process under the chip was more accurate when considering the capillary force. The effect of design factors is evaluated in this paper. The results show that the most important factors for void size are fluid viscosity, the gap height under the chip, transfer time, contact angle between the fluid and the contact surfaces, and transfer pressure. Specifically, a smaller gap height beneath the chip aggravates void formation, while lower viscosity, extended transfer time, reduced contact angle, and increased transfer pressure are effective in minimizing void size. The overall results of this study will be useful for product and process design in selecting appropriate solutions for IC packaging, particularly in the development of void-free molded-underfill flip-chip packages. These findings support the optimization of industrial packaging processes in semiconductor manufacturing by guiding material selection and process parameters, ultimately enhancing package reliability and yield.