Study of fine patterning lithography for panel level packaging

Heterogeneous integration is evolving to acquire finer resolution and larger devices to leverage the advantages provided by more-than-Moore manufacturing and packaging technologies that can help maximize the efficiency and increase the bandwidth of high performance computing systems. 2.xD integration with redistribution layers and large package sizes is one of solutions that can enable complex heterogeneous integration designs for applications, including artificial intelligence, 5G communication, and autonomous driving. For systems requiring large package sizes, panel level packaging (PLP) can offer efficiency and cost advantages over wafer level packaging. PLP, however, poses unique technical challenges, including the requirement to realize uniform fine patterning across the entire rectangular panel. In this paper, we report on our study of resolution and overlay performance using the panel stepper including an introduction of technology innovations supporting 2.xD heterogeneous integration development.