A five mask CMOS LTPS process with LDD and only one ion implantation step

Abstract We have developed a CMOS LTPS process which requires only five photolithographic masks and only one ion doping step. Drain/Source areas of NMOS TFTs were formed by PECVD deposition of a highly doped precursor layer while PMOS contact areas were defined by ion implantation. Single TFTs, inverters, ring oscillators and shift registers were fabricated. Nand p‐channel devices reached field effect mobilities of 173cm2/Vs and 47cm2/Vs, respectively.