Space charge limited conduction in CdSe thin films

The current (I)-voltage (V) characteristics of thermally evaporated CdSe thin films having thickness in the range 850–3000 A and deposited within the substrate temperature of 303–573 K show nearly linear dependence at low voltage and afterwards a non-linear behaviour at higher voltage range. A detailed study ofI-V curves in dark and under illumination clearly reveals the mechanism as ohmic at low voltage and that of trap limited space charge limited conduction (SCLC) at higher voltage. The transition voltage (Vt) from ohmic to SCLC is found to be quite independent of ambient temperature as well as intensity of illumination. SCLC is explained on the basis of the exponential trap distribution in CdSe films. Trap depths estimated from the lnI vs 103/T plots are found to be within 0.60-0.37 eV. Using the relevant SCLC theory, the carrier concentration, n0, total trap concentration, Nt, and the ratio of free charge to trapped charge, θ, have been calculated and correlated with ambient temperature and intensity of illumination.