journal article·2007-02-23

Wafer-Lever Hermetic Package with Through-Wafer Interconnects

Wang Yu-Chuan, Zhu Da-Peng, Xu Wei, Le Luo

Journal of Electronic Materials· Volume 36· Issue 2
Publisher page

Abstract

This paper reports a new wafer-level hermetic packaging structure with the features of low processing cost and high I/O density by using wet and dry sequentially etched through-wafer vias for the interconnects of a microelectro mechanical systems (MEMS) device. A thin Si wafer cap and wafer-level fabrication processes such as deep reactive ion etching (DRIE) and KOH etching, bottom-up copper filling, and Sn solder bonding were adopted. The hermeticity and bonding strength of the structure are evaluated. Preliminary results show that the hermeticity can meet the requirement of the criterion of MIL-STD 883E, method 1014.9, and the bonding strength is up to 8 MPa.
Source: openaire · Quality: candidate unverified · Source record ↗

Research context

OpenAlex topics: 3D IC and TSV technologies · Advanced MEMS and NEMS Technologies · Electronic Packaging and Soldering Technologies

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

References (7)

Show source-provided references
1. Garrou P. (2000) Wafer-Level Packaging Has Arrived Semiconductor International, p. 119
2. Satoh Akinobu. (2000) Jpn J Appl Phys 39:161210.1143/JJAP.39.1612 ↗
3. Satoshi Yamamoto (2003) Proc. 16th IEEE MEMS pp. 642–645
4. Chow Eugene M. (2002) J Microelectromech Systems 11:63110.1109/JMEMS.2002.805206 ↗
5. Joyce H. Wu (2000) IEEE IEDM pp. 477–480
6. Andricacos P.C., Uzoh C. (1998) IBM J Res Develop 42:56710.1147/rd.425.0567 ↗
7. MIL STD 883E, method 1014.9