journal article·2026-07-03Open access

Simulation Study of Short Channel Effects in New Hemispherical Gate-All-Around (HGAA) MOS Devices

Francis Balestra, Gerard Ghibaudo

Applied Sciences· Volume 16· Issue 13

Abstract

This work presents a numerical simulation study of short-channel effect (SCE) in new hemispherical gate-all-around (HGAA) MOS devices. These new HGAA architectures enable the optimization of the gate-electrostatic control of simple GAA MOS devices after rounding their channel’s edges to a well-defined radius of curvature. The simulation results indicate that the short-channel effects (SCEs) measured in terms of subthreshold swing SS and DIBL can be significantly improved in HGAA structures with a smaller silicon curvature radius. It is also found that the gate silicon surface area can be analytically calculated using the Pappus–Guldin theorem and used to model the gate oxide capacitance of such HGAA MOS devices. Pure spherical HGAA structures are also simulated and compared to simple HGAA structures, revealing their excellent performance in terms of SCE, making them an optimal 3D geometry architecture for CMOS integration with the best electrostatic control.
Source: crossref · Quality: baseline

Research context

OpenAlex topics: Advancements in Semiconductor Devices and Circuit Design · Semiconductor materials and devices · Electrostatic Discharge in Electronics

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

Affiliations

CROMA, Grenoble INP-Minatec, CNRS, University Grenoble Alpes, Parvis Louis Neel, 38000 Grenoble, France

References (22)

Show source-provided references
1. Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance10.1109/EDL.1987.26677 ↗
2. Hisamoto, D., Kaga, T., Kawamoto, Y., and Takeda, E. (1989). A fully depleted lean-channel transistor (DELTA)—A novel vertical ultra thin SOI MOSFET. Proceedings of the International Technical Digest on Electron Devices Meeting, IEEE.10.1109/55.46923 ↗
3. Yelp, G., Lin, S.S., Chen, Y.M., Shang, H.L., Wang, P.W., Lin, H.C., Peng, Y.C., Sheu, J.Y., Wang, M., and Chen, X. (2019). 5 nm CMOS production technology platform featuring full-fledged EUV and high mobility channel FinFETs with densest 0.021 μm2 SRAM cells for mobile SoC and high performance computing applications. Proceedings of the 2019 IEEE International Electron Devices Meeting (IEDM), IEEE.
4. Colinge, J.P., Gao, M.H., Romano-Rodriguez, A., Maes, H., and Claeys, C. (1990). Silicon-On-Insulator Gate-All-Around Device. Proceedings of the International Technical Digest on Electron Devices Meeting, IEEE.10.1109/IEDM.1990.237128 ↗
5. Bae, G., Bae, D.-I., Kang, M., Hwang, S.M., Kim, S.S., Seo, B., Kwon, T.Y., Lee, T.J., Moon, C., and Choi, Y.M. (2018). 3 nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications. Proceedings of the 2018 IEEE International Electron Devices Meeting (IEDM), IEEE.10.1109/IEDM.2018.8614629 ↗
6. (2026, May 01). IEEE IRDS Roadmap. Available online: https://irds.ieee.org/editions/2024/.
7. A novel Field Effect Transistor Architecture-The GAIA MOSFET10.1088/2631-8695/ae6547 ↗
8. Lilienfield, J.E. (1930). Method and Apparatus for Controlling Electric Currents. (1,745,175), U.S. Patent, Available online: https://fr.scribd.com/document/438543188/Us-1745175.
9. Wafer-Scale 3D Shaping of High Aspect Ratio Structures by Multistep Plasma Etching and Corner Lithography10.1038/s41378-020-0134-6 ↗
10. A Comprehensive Review on Convex and Concave Corners in Silicon Bulk Micromachining Based on Anisotropic Wet Chemical Etching10.1186/s40486-015-0012-4 ↗
11. Nonplanar Oxidation and Reduction of Oxide Leakage Currents at Silicon Corners by Rounding-Off Oxidation10.1109/T-ED.1987.23137 ↗
12. Adjustable Silicon Corner Rounding Radius by Wet Technique10.1149/MA2018-01/22/1398 ↗
13. PDE Solutions Inc (2026, May 01). Flexpde Software, version 6; PDE Solutions Inc.: Spokane, WA, USA, 2023. Available online: https://www.pdesolutions.com/.
14. Numerical simulation of electro-thermal properties in FDSOI MOSFETs down to deep cryogenic temperatures
15. Tsividis, Y., and McAndrew, C. (2011). Operation and Modeling of the MOS Transistor, Oxford University Press.
16. Critical MOSFETs operation for low voltage/low power IC’s: Ideal characteristics, parameter extraction, electrical noise and RTS fluctuations10.1016/S0167-9317(97)00166-4 ↗
17. Mohamad, B., Ghibaudo, G., Leroux, C., Josse, E., and Reimbold, G. (2015). Full Front and Back Split C-V characterization of CMOS devices from 14nm node FDSOI technology. Proceedings of the IEEE S3S Conference, IEEE.10.1109/S3S.2015.7333546 ↗
18. Pappus-Guldin theorems applied the study of solid modeling with GeoGebra software
19. (2026, May 01). Pappus’s Centroid Theorem in Wikipedia. Available online: https://en.wikipedia.org/wiki/Pappus%27s_centroid_theorem.
20. (2026, May 01). Capacitance in Wikipedia. Available online: https://en.wikipedia.org/wiki/Capacitance.
21. Taur, Y., and Ning, T.H. (1998). Fundamentals of Modern VLSI Devices, Cambridge University Press.
22. Simple and efficient MASTAR threshold voltage and subthreshold slope models for low-doped double-gate MOSFET10.1109/TED.2012.2201942 ↗