journal article·2026-06-24Open access

Validity of Cross-HDL Coding-Style Comparisons on Open-Source FPGA Toolchains: A Fabric-Domain Characterization of Synthesis Canonicalization

Vitaliy Kulanov, Artem Perepelitsyn

Applied Sciences· Volume 16· Issue 13

Abstract

Field-Programmable Gate Array (FPGA) technology allows for the creation of unique hardware implementations based on mass-produced chips. The process of project prototyping for such systems using Hardware Description Languages (HDLs) remains complex, even with modern tools. The comparison of HDL coding styles, for example, a behavioral case statement against a structural binary-tree decomposition, shows that the choice is capable of affecting post-implementation timing and area. The performed study, using the open-source yosys/nextpnr toolchain, shows that the validity of such a comparison is decided by the fabric domain. Logic that falls through to generic Look-Up Table (LUT) mapping is governed by the mapper’s heuristic fixed point rather than by source intent: on the crossbar, the behavioral and structural netlists become identical in cell composition; on the priority encoder, the verdict reverses; and on the barrel shifter, the LUT area collapses, so the comparison does not isolate the coding-style variable. It was measured that the keep_hierarchy attribute restores a meaningful comparison at ~17% LUT cost (N = 8) and provides a structural invariant to the ABC mapper variant, but the behavioral result is mapper-sensitive and the N = 4 verdict reverses under the legacy -noabc9 mapper (Cohen’s d from +2.4 to −1.6). By contrast, logic that involves a dedicated primitive before LUT mapping—an adder bound to the carry chain or a multiplier bound to a DSP block—yields source-meaningful verdicts that do not reverse with a mapper. Replication on a second fabric (Lattice iCE40) confirms that this behavior is fabric- rather than vendor-specific. The main contribution of this work is the proposed first fabric-domain characterization of synthesis canonicalization as a methodological hazard for cross-HDL FPGA studies on open-source toolchains, which identifies the two-phase synthesis mechanism that delimits it and supplies a decision rule (inspect post-synthesis composition) to identify whether a given comparison is susceptible.
Source: crossref · Quality: baseline

Research context

OpenAlex topics: Embedded Systems Design Techniques · Formal Methods in Verification · Parallel Computing and Optimization Techniques

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

Affiliations

Department of Computer Systems, Networks and Cybersecurity, National Aerospace University “KhAI”, 17, Chkalov Str., 61070 Kharkiv, Ukraine

References (27)

Show source-provided references
1. NanoXplore, STMicroelectronics (2026, May 14). NanoXplore and STMicroelectronics Deliver European FPGA for Space Missions, First to Qualify to New Europe-an ESCC 9030 Standard for Space Applications. Available online: https://nanoxplore.com/press-realease/nanoxplore-and-stmicroelectronics-deliver-european-fpga-for-space-missions/.
2. Danard, E., and Le Penven, M. (2023). NG-Ultra Application Development Ecosystem. Proceedings of the 2023 European Data Handling & Data Processing Conference (EDHPC), Juan Les Pins, France, 2–6 October 2023, IEEE.10.23919/EDHPC59100.2023.10396070 ↗
3. Shah, D., Hung, E., Wolf, C., Bazanski, S., Gisselquist, D., and Milanovic, M. (2019). Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs. Proceedings of the 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), San Diego, CA, USA, 28 April–1 May 2019, IEEE.10.1109/FCCM.2019.00010 ↗
4. Atwell, I.D., and Perera, D.G. (2024). HDL Code Variation: Impact on FPGA Performance Metrics and CAD Tools. Proceedings of the 2024 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), Victoria, BC, Canada, 21–24 August 2024, IEEE.10.1109/PACRIM61180.2024.10690218 ↗
5. Zhang, Y., Jiang, H., Guo, S., Li, X., Liu, H., and Shi, C. (2025). Toward Understanding FPGA Synthesis Tool Bugs. ACM Trans. Softw. Eng. Methodol., 34.10.1145/3718737 ↗
6. Herklotz, Y., and Wickerson, J. (2020). Finding and Understanding Bugs in FPGA Synthesis Tools. Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA ’20), Association for Computing Machinery.10.1145/3373087.3375310 ↗
7. Insights From Bugs in FPGA High-Level Synthesis Tools: An Empirical Study of Bambu Bugs10.1109/TR.2025.3547739 ↗
8. Cosgrove, O., Donaldson, A.F., and Wickerson, J. (2026). Finding and Understanding Bugs in FPGA Place-and-Route Engines. Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA ’26), Association for Computing Machinery.10.1145/3748173.3779185 ↗
9. (2026, May 14). cocotb. Available online: https://www.cocotb.org/.
10. Improvements to Technology Mapping for LUT-Based FPGAs10.1109/TCAD.2006.887925 ↗
11. FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs10.1109/43.273754 ↗
12. Chen, D., and Cong, J. (2004). DAOmap: A depth-optimal area optimization mapping algorithm for FPGA designs. Proceedings of the IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, USA, 7–11 November 2004, IEEE. ICCAD-2004.10.1109/ICCAD.2004.1382677 ↗
13. Hofmann, M., Gokmen, B., and Zhang, Z. (2025). EqMap: FPGA LUT Remapping using E-Graphs. Proceedings of the 2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD), Munich, Germany, 26–30 October 2025, IEEE.10.1109/ICCAD66269.2025.11240672 ↗
14. Lu, S., Shang, L., Qu, Q., Jung, S., Liang, Q., and Pan, C. (2025). An Efficient Multi-Output LUT Mapping Technique for Field-Programmable Gate Arrays. Electronics, 14.10.3390/electronics14091782 ↗
15. Zhou, G., and Anderson, J.H. (2023). Area-Driven FPGA Logic Synthesis Using Reinforcement Learning. Proceedings of the 2023 28th Asia and South Pacific Design Automation Conference (ASPDAC ’23), Tokyo, Japan, 16–19 January 2023, Association for Computing Machinery.10.1145/3566097.3567894 ↗
16. Gort, M., and Anderson, J.H. (2012). Analytical placement for heterogeneous FPGAs. Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, 29–31 August 2012, IEEE.10.1109/FPL.2012.6339278 ↗
17. Luk, W., Cheung, P.Y.K., and Glesner, M. (1997). VPR: A new packing, placement and routing tool for FPGA research. Field-Programmable Logic and Applications, Springer. FPL 1997; Lecture Notes in Computer Science.10.1007/3-540-63465-7 ↗
18. GHDL (2026, May 14). ghdl-yosys-plugin: VHDL Synthesis (Based on GHDL and Yosys). Available online: https://github.com/ghdl/ghdl-yosys-plugin.
19. (2026, May 14). OSS CAD Suite. Available online: https://github.com/YosysHQ/oss-cad-suite-build.
20. (2026, May 14). Yosys Open SYnthesis Suite. Available online: https://yosyshq.net/yosys/.
21. Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures10.1007/978-3-319-01418-0_12 ↗
22. (2026, May 14). Project Trellis. Available online: https://github.com/YosysHQ/prjtrellis.
23. Lattice Semiconductor Corporation (2026, May 14). ECP5/ECP5-5G—Ultra Low Power FPGA. Available online: https://www.latticesemi.com/Products/FPGAandCPLD/ECP5.
24. Fibich, C., and Lovric, L. (2025). Leveraging Open-Source Bitstream Documentation for FPGA Soft-Error Robustness Analysis. Proceedings of the 2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS), Ischia, Italy, 7–9 July 2025, IEEE.10.1109/IOLTS65288.2025.11116854 ↗
25. Ismail, N.M.H., and Omran, M.G.H. (2026). Beyond Significance: Promoting Effect Size Measures in Comparing Metaheuristic Algorithms. Algorithms, 19.10.3390/a19030191 ↗
26. Heijungs, R., Henriksson, P.J.G., and Guinée, J.B. (2016). Measures of Difference and Significance in the Era of Computer Simulations, Meta-Analysis, and Big Data. Entropy, 18.10.3390/e18100361 ↗
27. Mishchenko, A., Chatterjee, S., and Brayton, R. (2006). DAG-aware AIG rewriting a fresh look at combinational logic synthesis. Proceedings of the 43rd annual Design Automation Conference (DAC ’06), Association for Computing Machinery.10.1145/1146909.1147048 ↗