Statistical Sequential Path Delay Variation Model with Lognormal Distribution for Low-Voltage Circuit
Source abstract
Abstract
To solve the timing uncertainty in low-voltage circuits, this paper proposes an analytical sequential path delay model based on the lognormal distribution. Unlike previous works that primarily focus on combinational logic, our model provides a complete framework for sequential elements. It decouples inter-stage correlations within flip-flops through a linear delay transformation. The model’s key innovation is a one-shot characterization approach that dramatically reduces simulation time compared to traditional Monte Carlo methods. All experiments on the TSMC 28 nm process show high accuracy, with average errors below 6% against MC. Our model demonstrates significant prediction accuracy improvements of up to 10.2X over prior art, establishing a highly efficient and accurate solution for variation-aware sequential timing analysis.
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Research context
OpenAlex topics: Low-power high-performance VLSI design · VLSI and FPGA Design Techniques · VLSI and Analog Circuit Testing
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
College of Integrated Circuit Science and Engineering (College of Industry-Education Integration), Nanjing University Posts and Telecommunications, Nanjing 210023, China
Funding
National Natural Science Foundation of China · Natural Science Foundation of Jiangsu Province
References (26)
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