Error Mitigation Methods for FSM Using Triple Modular Redundancy
Source abstract
Abstract
In many areas of operation, application-specific logic implemented in FPGAs (Field Programmable Gate Arrays) is critical. In these situations, various mitigation methods are used to reduce or completely eliminate malfunctions in the circuit resulting from undesired physical phenomena (e.g., ionizing radiation). Such phenomena may occur, among others, in medicine, the military, nuclear power, and space systems. One of the most popular methods is the use of triple modular redundancy (TMR). Here, the FPGA provides a good basis for building TMR-based safety-critical systems due to its concurrent processing. This paper presents an overview of the implementation of logic structures using TMR. In this paper, the authors focus on different concepts for the implementation of FSMs. The different concepts differ in the way TMR voters are attached and the extent of redundancy of the individual FSM components. The article compares the efficiency of the different solutions. In order to evaluate this efficiency, it is crucial to determine the logic utilization or the power consumption of a given implementation. In the experimental part of the article, the authors show the results of the synthesis of FSM benchmarks, for different mitigation models. The synthesis was carried out for both commercial and academic tools.
Source: crossref · Quality: baseline
Research context
OpenAlex topics: VLSI and Analog Circuit Testing · Integrated Circuits and Semiconductor Failure Analysis · Semiconductor materials and devices
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
Department of Digital Systems, Silesian University of Technology, ul. Akademicka 2A, 44-100 Gliwice, Poland
KP Labs, Bojkowska Str. 37J, 44-100 Gliwice, Poland
Funding
European Space Agency · Polish Ministry of Science and Higher Education funding for statutory activities
References (60)
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1. Galkin, P., Umiarov, R., Grigorieva, O., and Ageyev, D. (2019, January 8–11). Approaches for Safety-Critical Embedded Systems and Telecommunication Systems Design for Avionics Based on FPGA. Proceedings of the 2019 IEEE International Scientific-Practical Conference Problems of Infocommunications, Science and Technology (PIC S&T), Kyiv, Ukraine.10.1109/PICST47496.2019.9061421 ↗
2. Ball, J.E., and Tang, B. (2019). Machine Learning and Embedded Computing in Advanced Driver Assistance Systems (ADAS). Electronics, 8.10.3390/electronics8070748 ↗
3. Baumann, R., and Kruckmeyer, K. (2020). Radiation Handbook for Electronics, Texas Instruments.
4. White, D. (2012). Considerations Surrounding Single Event Effects in FPGAs, ASICs, and Processors, Xilinx Inc.. [v1.0.1 ed.].
5. Hatefinasab, S., Rodriguez, N., García, A., and Castillo, E. (2021). Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit. Electronics, 10.10.3390/electronics10111256 ↗
6. Actel (2010). Radiation-Tolerant ProASIC3 FPGAs Radiation Effects, Actel.
7. Adell, P., and Allen, G. (2008). Assessing and Mitigating Radiation Effects in Xilinx FPGAs, Jet Propulsion Laboratory. Technical Report.10.1109/RADECS.2008.5782755 ↗
8. Hall, F. (2013). Fault Tolerant Design Implementation on Radiation Hardened by Design SRAM-Based FPGAs. [Master’s Thesis, Massachusetts Institute of Technology]. Available online: https://dspace.mit.edu/handle/1721.1/82490.
9. Zheng, S., You, H., He, G., Wang, Q., Si, T., Jiang, J., Jin, J., and Jing, N. (2019, January 26–29). A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan.10.1109/ISCAS.2019.8702706 ↗
10. Kumar, M., Digdarsini, D., Misra, N., and Ram, T.V.S. (2017, January 2–3). SEU mitigation of Rad-Tolerant Xilinx FPGA using external scrubbing for geostationary mission. Proceedings of the 4th International Conference on Signal Processing and Integrated Networks (SPIN), Noida, India.10.1109/SPIN.2017.8049985 ↗
11. Ruano, Ó., García-Herrero, F., Aranda, L., Sánchez-Macián, A., Rodriguez, L., and Maestro, J. (2021). Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial. Sensors, 21.10.3390/s21041392 ↗
12. He, W., Wang, Y., Xing, K., and Chen, L. (2011, January 10–12). SEU readback interval strategy of SRAM-based FPGA for space application. Proceedings of the IEEE International Conference on Computer Science and Automation Engineering, Shanghai, China.10.1109/CSAE.2011.5952842 ↗
13. Gantel, L., Berthet, Q., Amri, E., Karlov, A., and Upegui, A. (2021). Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application. Electronics, 10.10.3390/electronics10172148 ↗
14. Low Latency SEU Detection in FPGA CRAM with In-Memory ECC Checking10.1109/TCSI.2023.3243644 ↗
15. Error detecting and error correcting codes10.1002/j.1538-7305.1950.tb00463.x ↗
16. Polynomial Codes over Certain Finite Fields10.1137/0108018 ↗
17. Leong, C., Semião, J., Santos, M., Teixeira, I., Teixeira, J., Batista, A., Gonçalves, B., and Marques, J. (2015, January 25–27). Fast radiation monitoring in FPGA-based designs. Proceedings of the 2015 Conference on Design of Circuits and Integrated Systems (DCIS), Estoril, Portugal.10.1109/DCIS.2015.7388590 ↗
18. Mahmoud, D.G., Alkady, G.I., Amer, H.H., Daoud, R.M., Adly, I., Essam, Y., Ismail, H.A., and Sorour, K.N. (2018, January 10–14). Fault secure FPGA-based TMR voter. Proceedings of the 7th Mediterranean Conference on Embedded Computing (MECO), Budva, Montenegro.10.1109/MECO.2018.8406016 ↗
19. Benites, L.A.C., and Kastensmidt, F.L. (2018, January 12–14). Automated design flow for applying Triple Modular Redundancy (TMR) in complex digital circuits. Proceedings of the IEEE 19th Latin-American Test Symposium (LATS), Sao Paulo, Brazil.10.1109/LATW.2018.8349668 ↗
20. General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework10.1109/TCSI.2021.3076185 ↗
21. Ruano, Ó., Maestro, J.A., and Reviriego, P. (2011, January 13–15). Validation and optimization of TMR protections for circuits in radiation environments. Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Cottbus, Germany.10.1109/DDECS.2011.5783120 ↗
22. Neutron Radiation Testing of RISC-V TMR Soft Processors on SRAM-Based FPGAs10.1109/TNS.2023.3235582 ↗
23. FPGA-Based Reconfigurable Control for Fault-Tolerant Back-to-Back Converter Without Redundancy10.1109/TIE.2012.2200214 ↗
24. Improving characteristics of LUT-based Moore FSMs10.1109/ACCESS.2020.3006732 ↗
25. Improving characteristic of LUT-based Mealy FSMs10.34768/amcs-2020-0055 ↗
26. Kubica, M., Opara, A., and Kania, D. (2021). Technology Mapping for LUT-Based FPGA, Springer.10.1007/978-3-030-60488-2 ↗
27. Salauyou, V. (2024). Area and Performance Estimates of Finite State Machines in Reconfigurable Systems. Appl. Sci., 14.10.3390/app142411833 ↗
28. Cheng, L., Chen, D., and Wong, M.D.F. (2007, January 4–8). DDBDD: Delay-Driven BDD Synthesis for FPGAs. Proceedings of the 44th ACM/IEEE Design Automation Conference, San Diego, CA, USA.10.1145/1278480.1278705 ↗
29. Kubica, M., Opara, A., and Kania, D. (2021). Logic Synthesis Strategy Oriented to Low Power Optimization. Appl. Sci., 11.10.3390/app11198797 ↗
30. Decomposition Approaches for Power Reduction10.1109/ACCESS.2023.3260970 ↗
31. Technology mapping of multi–output functions leading to the reduction of dynamic power consumption in FPGAs10.34768/amcs-2023-0020 ↗
32. Chattopadhyay, S., Yadav, P., and Singh, R. (2004, January 20–22). Multiplexer Targeted Finite State Machine Encoding for Area and Power Minimization. Proceedings of the IEEE INDICON, India Annual Conference, Kharagpur, India.
33. Kajstura, K., and Kania, D. (2016, January 17–20). Binary Tree-based Low Power State Assignment Algorithm. Proceedings of the 12-th International Conference of Computational Methods in Science and Engineering, ICCMSE 2016, Athens, Greece.
34. Amin, R.A., Amran Hossain, M.S., Schmid, L.T., Wiese, V., and Obermaisser, R. (2024, January 8–11). Power Efficient Real-Time Traffic Signal Classification for Autonomous Driving Using FPGAs. Proceedings of the 2024 6th International Conference on Communications, Signal Processing, and Their Applications (ICCSPA), Istanbul, Turkiye.10.1109/ICCSPA61559.2024.10794303 ↗
35. Khan, M.I., and da Silva, B. (2024). Harnessing FPGA Technology for Energy-Efficient Wearable Medical Devices. Electronics, 13.10.3390/electronics13204094 ↗
36. Low Power Synthesis and Validation of an Embedded Multiplier for FPGA Based Wireless Communication Systems10.1007/s11277-016-3897-1 ↗
37. Kim, Y., Kim, H., Yadav, N., Li, S., and Choi, K.K. (2020). Low-Power RTL Code Generation for Advanced CNN Algorithms toward Object Detection in Autonomous Vehicles. Electronics, 9.10.3390/electronics9030478 ↗
38. Kubica, M., and Czerwinski, R. (2024). Performance Testing of the Triple Modular Redundancy Mitigation Circuit Test Environment Implementation in Field Programmable Gate Array Structures. Appl. Sci., 14.10.3390/app14198604 ↗
39. Aguiar, Y.Q.d., Wrobel, F., Autran, J.L., and García Alía, R. (2025). Introduction to Single-Event Effects. Single-Event Effects, from Space to Accelerator Environments:Analysis, Prediction and Hardening by Design, Springer International Publishing.10.1007/978-3-031-71723-9 ↗
40. Single Event Transient on Combinational Logic: An Introduction and their Mitigation
41. Wang, J. (October, January 29). Radiation effects in FPGAs. Proceedings of the 9th Workshop on Electronics for LHC Experiments, Amsterdam, The Netherlands.
42. Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits10.1016/j.microrel.2009.08.001 ↗
43. Balasubramanian, P., and Prasad, K. (2017). A Fault Tolerance Improved Majority Voter for TMR System Architectures. arXiv.
44. Ban, T., and de Barros Naviner, L.A. (2010, January 20–23). A simple fault-tolerant digital voter circuit in TMR nanoarchitectures. Proceedings of the Proceedings of the 8th IEEE International NEWCAS Conference 2010, Montreal, QC, Canada.10.1109/NEWCAS.2010.5603933 ↗
45. Deepa, M., and Beulet, P.A.S. (2022, January 11–12). An Improvised Voter Architecture for TMR with Reduced Area Overhead. Proceedings of the 2022 Third International Conference on Intelligent Computing Instrumentation and Control Technologies (ICICICT), Kannur, India.
46. A Self-Checking TMR Voter for Increased Reliability Consensus Voting in FPGAs10.1109/TNS.2018.2824821 ↗
47. Girardey, R., Hübner, M., and Becker, J. (2010, January 5–7). Mixed-Signal Diverse Redundant System for Safety Critical Applications in FPGA. Proceedings of the 2010 IEEE Computer Society Annual Symposium on VLSI, Lixouri, Greece.10.1109/ISVLSI.2010.11 ↗
48. Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems10.1109/TVLSI.2012.2213102 ↗
49. Liu, J., Li, X., Zhang, J., and Li, J. (2022, January 22–25). An Area-Efficient Design of Enhanced Space-Time Redundant DFF (IEST_TMR DFF). Proceedings of the 7th International Conference on Computer and Communication Systems (ICCCS), Wuhan, China.10.1109/ICCCS55155.2022.9846117 ↗
50. Gomes, I.A.C., Martins, M., Reis, A., and Kastensmidt, F.L. (2015, January 25–27). Using only redundant modules with approximate logic to reduce drastically area overhead in TMR. Proceedings of the 16th Latin-American Test Symposium (LATS), Puerto Vallarta, Mexico.10.1109/LATW.2015.7102522 ↗
51. A Comparison of TMR with Alternative Fault-Tolerant Design Techniques for FPGAs10.1109/TNS.2007.910871 ↗
52. A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance10.1155/2017/5419767 ↗
53. Hamamatsu, M., Tsuchiya, T., and Kikuno, T. (2008, January 15–17). Finding the Optimal Configuration of a Cascading TMR System. Proceedings of the 2008 14th IEEE Pacific Rim International Symposium on Dependable Computing, Taipei, Taiwan.10.1109/PRDC.2008.12 ↗
54. Khan, K., and Zuiss, B. (2023). Verifying Safety-Critical FPGA Designs with Fault Simulation and Injection, Synopsys. White Paper.
55. Khan, K., and Hoskins, D. (2023). Functional Safety for FPGA-Based Hardware Designs, Synopsys. White Paper.
56. Cassel, M., and Lima, F. (2006, January 10–12). Evaluating one-hot encoding finite state machines for SEU reliability in SRAM-based FPGAs. Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS’06), Lake Como, Italy.
57. te Slaa, P.S. (2020). Fault Tolerant Techniques for Finite State Machines in Hardware Designs. [Master’s Thesis, Eindhoven University of Technology].
58. Petrovic, V., and Krstic, M. (2015, January 22–24). Design Flow for Radhard TMR Flip-Flops. Proceedings of the 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, Belgrade, Serbia.10.1109/DDECS.2015.65 ↗
59. Collaborative Benchmarking and Experimental Algorythmics Laboratory (2008). LGSynth93 Benchmarks, Collaborative Benchmarking and Experimental Algorythmics Laboratory.
60. Berkeley Logic Synthesis Group (2005). ABC: A System for Sequential Synthesis and Verification, Berkeley Logic Synthesis Group.