A 13.44-Bit Low-Power SAR ADC for Brain–Computer Interface Applications
Source abstract
Abstract
This paper presents a successive approximation register analog-to-digital converter (SAR ADC) specifically optimized for brain–computer interface (BCI) applications. Designed and post-layout-simulated using 180 nm CMOS technology, the proposed SAR ADC achieves a 13.44-bit effective number of bits (ENOB) and 27.9 μW of power consumption at a supply voltage of 1.8 V, enabled by a piecewise monotonic switching scheme and dynamic logic architecture. The ADC supports a high input range of ±500 mV, making it suitable for neural signal acquisition. Through an optimized capacitive digital-to-analog converter (CDAC) array and a high-speed dynamic comparator, the ADC demonstrates a signal-to-noise-and-distortion ratio (SINAD) of 81.94 dB and a spurious-free dynamic range (SFDR) of 91.69 dBc at a sampling rate of 320 kS/s. Experimental results validate the design’s superior performance in terms of low-power operation, high resolution, and moderate sampling rate, positioning it as a competitive solution for high-density integration and precision neural signal processing in next-generation BCI systems.
Source: crossref · Quality: baseline
Research context
OpenAlex topics: Neuroscience and Neural Engineering · EEG and Brain-Computer Interfaces · Advanced Memory and Neural Computing
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
School of Microelectronics, Shanghai University, Shanghai 201800, China
MTRIX Corporation, Shanghai 201800, China
Funding
Lingang Laboratory
References (21)
Show source-provided references
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