journal article·2025-04-05Open access

Study on Single-Event Transient Hardness of Semi-Enclosed Gate NMOS

Zhuoxiang Wang, Gang Li, Minghua Tang

Applied Sciences· Volume 15· Issue 7

Abstract

Based on the simulation software, single-event transient (SET) simulations were conducted on semi-enclosed gate NMOS devices. The simulation involved bombarding the semi-enclosed gate NMOS devices with heavy ions under specific conditions. A comparative analysis was conducted to evaluate the single-event transient tolerance of traditional NMOS and semi-enclosed gate NMOS. Simulation curves from transient to steady-state states under different Linear Energy Transfer (LET) values, as well as potential distribution and current density distribution maps following heavy ion bombardment, were analyzed. Furthermore, single-event transient simulations were carried out on inverters composed of both NMOS types, with subsequent analysis. The results ultimately demonstrate that the semi-enclosed gate NMOS exhibits superior single-event transient tolerance compared to conventional NMOS.
Source: crossref · Quality: baseline

Research context

OpenAlex topics: Radiation Effects in Electronics · Semiconductor materials and devices · Advanced Memory and Neural Computing

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

Affiliations

School of Materials Science and Engineering, Xiangtan University, Xiangtan 411105, China

Funding

National Key Research and Development Program of China · National Natural Science Foundation of China · Hunan Provincial Natural Science Foundation

References (35)

Show source-provided references
1. The influence with reliability of motional satellite by the single-event phenomena
2. Chen, P. (2005). Radiation Effects on Semiconductor Devices and Integrated Circuits, National Defense Industry Press.
3. Space radiation effects and reliability considerations for micro- and optoelectronic devices10.1109/TDMR.2010.2048111 ↗
4. Koons, H.C. (1998, January 5–9). The impact of the space environment on space systems. Proceedings of the 6th Space Charging Technology Conference, Como, Italy.
5. Tribble, A.C. (1993, January 11–14). The space environment and its impact on spacecraft design. Proceedings of the AIAA Aerospace Sciences Meeting & Exhibit 31st AIAA Aerospace Sciences Meeting and Exhibit, Reno, NV, USA.10.2514/6.1993-491 ↗
6. Darrin, M.A.G. (2005, January 23). The impact of the space radiation environment on micro electro mechanical systems (MEMS) and microstructures. Proceedings of the European Conference on Radiation & Its Effects on Components & Systems, Cap d’Agde, France.
7. Schott, J.U. (1991, January 9–12). Particle radiation effects in charge coupled devices (CCDs) with applications in single event experiments. Proceedings of the RADECS 91 First European Conference on Radiation and its Effects on Devices and Systems, Montpellier, France.
8. Massengill, L.W., Bhuva, B.L., Holman, W.T., Alles, M.L., and Loveless, T.D. (2012, January 15–19). Technology scaling and soft error reliability. Proceedings of the 2012 IEEE International Reliability Physics Symposium (IRPS), Anaheim, CA, USA.10.1109/IRPS.2012.6241810 ↗
9. Huard, V. (2015, January 7–9). Technology scaling and reliability: Challenges and opportunities. Proceedings of the 2015 IEEE International Electron Devices Meeting (IEDM), Washington, DC, USA.
10. Effect of well and substrate potential modulation on single event pulse shape in deep submicron CMOS10.1109/TNS.2007.910863 ↗
11. Comparison of heavy ion and proton induced combinatorial and sequential logic error rates in a deep submicron process10.1109/TNS.2005.860678 ↗
12. Comparison of combinational and sequential error rates for a deep submicron process10.1109/TNS.2011.2171993 ↗
13. Study of total ionizing dose radiation effects on enclosed gate transistors in a commercial CMOS technology10.1088/1009-1963/16/12/034 ↗
14. Creating a parameterized model of a CMOS transistor with a gate of enclosed layout10.1088/1742-6596/675/4/042043 ↗
15. Study and Analysis of Enclosed Gate FET’s10.1088/1757-899X/1104/1/012024 ↗
16. Simulation of Silicon FETs with a Fully Enclosed Gate with a High-k Gate Dielectric10.1134/S1063739723700361 ↗
17. CVC Simulation of Ultrathin Soi-Cmos Nanotransistors with a Fully Enclosed Gate10.1134/S1063739721050036 ↗
18. Degradation Induced by X-Ray Irradiation and Channel Hot Carrier Stresses in 130-nm NMOSFETs With Enclosed Layout10.1109/TNS.2008.2006747 ↗
19. Aspect ratio of radiation-hardened MOS transistors Modelling of the equivalent channel dimensions of integrated MOS transistors in radiation-hardened enclosed layout10.1007/s00502-017-0575-2 ↗
20. Total Dose Effects on Circuit Speed Measurements10.1109/TNS.1983.4333119 ↗
21. Pseudosymmetric Enclosed Layout Transistors for Radiation Hardened Analog Applications
22. Platcheck, P., Cardoso, G.S., and Balen, T.R. (2024, January 9–12). Behavioral and Variability Analysis of Enclosed Layout Transistors for Radiation Hardened Analog Circuits. Proceedings of the 2024 IEEE 25th Latin American Test Symposium (LATS), Maceio, Brazil.10.1109/LATS62223.2024.10534614 ↗
23. Analysis of single-event transients in analog circuits10.1109/23.903817 ↗
24. Development of a test methodology for single-event transients (SETs) in linear devices10.1109/23.983193 ↗
25. Studies of single-event transient current induced in GaAs and Si diodes by energetic heavy ions10.1016/S0969-806X(00)00360-1 ↗
26. Effect of amplifier parameters on single-event transients in an inverting operational amplifier10.1109/TNS.2002.1039690 ↗
27. Single event transient effects in a voltage reference10.1016/j.microrel.2004.05.029 ↗
28. Single-Event Transients in Bipolar Linear Integrated Circuits10.1109/TNS.2006.882497 ↗
29. Heavy ion and proton induced single event transients in comparators10.1109/23.556892 ↗
30. Pimingstorfer, H., Halama, S., and Selberherr, S. (2025, April 02). A TCAD Environment for Process and Process and Device Engineering. ICVC: International Conference on VLSI and CAD 2. Available online: https://www.iue.tuwien.ac.at/pdf/ib_1991/CP1991_Pimingstorfer_1.pdf.
31. TCAD: CHALLENGED TO VIRTUAL PROCESS
32. Total TCAD strategy for DFM in IC technology development10.1049/ip-smt:19970860 ↗
33. Accuracy counts in modeling TCAD’s future10.1109/45.876892 ↗
34. Dai, L. (2022). CMOS Integrated Circuit EDA Technology, China Machine Press. [2nd ed.].
35. 55 nm Logic Low Leakage 1.2 V/1.8 V/2.5 V and Ultra Low Power 0.9 V/1.8 V/2.5 V RF Calibre LVS Release Note 2016.