An Improved Low-Density Parity-Check Decoder and Its Field-Programmable Gate Array Implementation

Based on the IEEE 802.16e standard’s (672,336) LDPC code and the normalized Min-Sum decoding algorithm, this paper designs and implements an LDPC decoder that optimizes the channel information. The correction factor for check nodes is converted into a correction factor for the initial channel information, replacing the optimization of check node information with that of initial channel information. This achieves decoding performance equivalent to the traditional normalized Min-Sum decoding algorithm. Different correction factor values vary in complexity during FPGA implementation, as they involve different amounts of shift-add operations. For NMS decoding requiring a high number of shift-add operations to achieve optimal correction values, this can be converted into an LDPC decoding algorithm optimized for channel information, reducing computational overhead without sacrificing performance. A partially parallel improved decoder was designed and implemented on an FPGA, and its feasibility was verified using the Vivado simulation platform.